I am using ZCU102 board (Zynq Ultrascale+ MPSoC). I am sending the data (data packet) generating from custom HLS IP to 10G High speed subsystem without using AXI DMA. I am able to monitor the data in Wireshark but i want to measure the performance of the design. So, i have added Axi Performance monitor IP`s block into our design.
The platform used for Performance monitor is XSDK. While compiling the XSDK, the performance count of each read and write axis its showing "zero". Please anyone guide me how to implement the design with Axi Performance monitor.
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Thausikan
Hi,
I am using ZCU102 board (Zynq Ultrascale+ MPSoC). I am sending the data (data packet) generating from custom HLS IP to 10G High speed subsystem without using AXI DMA. I am able to monitor the data in Wireshark but i want to measure the performance of the design. So, i have added Axi Performance monitor IP`s block into our design.
The platform used for Performance monitor is XSDK. While compiling the XSDK, the performance count of each read and write axis its showing "zero". Please anyone guide me how to implement the design with Axi Performance monitor.
I have attached the screenshot what we tried.
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