Basys3 - memory adressing etc.

donwazonesko · December 17, 2018

Hello!

I've been trying to work with A/D converters and after a while i've finally understood how do they work. Now want to proceed my data to memory blocks. As far as i know i need to increment the given adress to be able to fulfill the whole memory cell. Could you please tell me how am i suppose to do it?

Here's my code..

Spoiler


entity MainFpga is
    Port( 
        dclk_in  : in STD_LOGIC;
        vp       : in STD_LOGIC;
        vn       : in STD_LOGIC;
        ena      : IN STD_LOGIC;
        wea      : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        addra    : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
        vauxp6   : IN STD_LOGIC;
        vauxn6   : IN STD_LOGIC;
        vauxp7   : IN STD_LOGIC;
        vauxn7   : IN STD_LOGIC;
        vauxp4   : in STD_LOGIC;
        vauxn4   : in STD_LOGIC;
        vauxp5   : in STD_LOGIC;
        vauxn5   : in STD_LOGIC;
        vauxp12  : in STD_LOGIC;
        vauxn12  : in STD_LOGIC;
        vauxp13  : in STD_LOGIC;
        vauxn13  : in STD_LOGIC;
        vauxp14  : in STD_LOGIC;
        vauxn14  : in STD_LOGIC;
        vauxp15  : in STD_LOGIC;
        vauxn15  : in STD_LOGIC);
end MainFpga;

architecture Behavioral of MainFpga is

signal  dina_1      :  STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_1     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_2      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_2     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_3      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_3     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_4      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_4     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_5      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_5     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_6      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_6     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_7      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_7     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  dina_8      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal  douta_8     : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal DataValid    : STD_LOGIC;
signal DataReady    : STD_LOGIC;
signal DataIn       : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal DataOut      : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal indeks       : integer := 0;

type adresy_pmod is array (0 to 7) of std_logic_vector(6 downto 0); 
constant adres : adresy_pmod :=("0010100","0010101","0010110","0010111","0011100","0011101","0011110","0011111"); 
-- 4/5/6/7/12/13/14/15 VAUXN/P ADRES

signal nr_adc : std_logic_vector(6 downto 0) := adres(0); 

COMPONENT Memory_12bit_4096
  PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;

COMPONENT xadc_wiz_0
  PORT (
    di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    daddr_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    den_in : IN STD_LOGIC;
    dwe_in : IN STD_LOGIC;
    drdy_out : OUT STD_LOGIC;
    do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    dclk_in : IN STD_LOGIC;
    reset_in : IN STD_LOGIC;
    vp_in : IN STD_LOGIC;
    vn_in : IN STD_LOGIC;
    vauxp4 : in STD_LOGIC;
    vauxn4 : in STD_LOGIC;
    vauxp5 : in STD_LOGIC;
    vauxn5 : in STD_LOGIC;
    vauxp6 : in STD_LOGIC;
    vauxn6 : in STD_LOGIC;
    vauxp7 : in STD_LOGIC;
    vauxn7 : in STD_LOGIC;
    vauxp12 : in STD_LOGIC;
    vauxn12 : in STD_LOGIC;
    vauxp13 : in STD_LOGIC;
    vauxn13 : in STD_LOGIC;
    vauxp14 : in STD_LOGIC;
    vauxn14 : in STD_LOGIC;
    vauxp15 : in STD_LOGIC;
    vauxn15 : in STD_LOGIC;
    channel_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
    eoc_out : OUT STD_LOGIC;
    alarm_out : OUT STD_LOGIC;
    eos_out : OUT STD_LOGIC;
    busy_out : OUT STD_LOGIC
  );
END COMPONENT;

begin

MyAdc : xadc_wiz_0
  PORT MAP (
    di_in => X"0000",
    daddr_in => nr_adc,
    den_in => DataValid,
    dwe_in => '0',
    drdy_out => DataReady,
    do_out => DataOut,
    dclk_in => dclk_in,
    reset_in => '0',
    vp_in => '0',
    vn_in => '0',
    vauxp4 => vauxp4,
    vauxn4 => vauxn4,
    vauxp5 => vauxp5,
    vauxn5 => vauxn5,
    vauxp6 => vauxp6,
    vauxn6 => vauxn6,
    vauxp7 => vauxp7,
    vauxn7 => vauxn7, 
    vauxp12 => vauxp12,
    vauxn12 => vauxn12,
    vauxp13 => vauxp13,
    vauxn13 => vauxn13,
    vauxp14 => vauxp14,
    vauxn14 => vauxn14,
    vauxp15 => vauxp15,
    vauxn15 => vauxn15,
    channel_out => open,
    eoc_out => DataValid,
    alarm_out => open,
    eos_out => open,
    busy_out => open
  );

MEM1  : Memory_12bit_4096
    PORT MAP(
        clka => dclk_in,
        ena => ena,
        wea => wea,
        addra => addra,
        dina => dina_1,
        douta => douta_1
    );  
    
MEM2  : Memory_12bit_4096
    PORT MAP(
        clka => dclk_in,
        ena => ena,
        wea => wea,
        addra => addra,
        dina => dina_2,
        douta => douta_2
    );
    
MEM3  : Memory_12bit_4096
    PORT MAP(
        clka => dclk_in,
        ena => ena,
        wea => wea,
        addra => addra,
        dina => dina_3,
        douta => douta_3
    );
    
MEM4  : Memory_12bit_4096
    PORT MAP(
        clka => dclk_in,
        ena => ena,
        wea => wea,
        addra => addra,
        dina => dina_4,
        douta => douta_4
    );
    
MEM5  : Memory_12bit_4096
    PORT MAP(
        clka => dclk_in,
        ena => ena,
        wea => wea,
        addra => addra,
        dina => dina_5,
        douta => douta_5
    );
    
 MEM6  : Memory_12bit_4096
    PORT MAP(
        clka => dclk_in,
        ena => ena,
        wea => wea,
        addra => addra,
        dina => dina_6,
        douta => douta_6
    );
    
 MEM7  : Memory_12bit_4096
       PORT MAP(
           clka => dclk_in,
           ena => ena,
           wea => wea,
           addra => addra,
           dina => dina_7,
           douta => douta_7
       );
       
 MEM8  : Memory_12bit_4096
          PORT MAP(
              clka => dclk_in,
              ena => ena,
              wea => wea,
              addra => addra,
              dina => dina_8,
              douta => douta_8
          );

OutputBuffer: process(dclk_in)
begin
  if(dclk_in'event and dclk_in = '1') then
    if(DataReady = '1') then       
        case nr_adc is
            when adres(0) =>   
                dina_1 <= DataOut;
            when adres(1) =>   
                dina_2 <= DataOut;
            when adres(2) =>   
                dina_3 <= DataOut;
            when adres(3) =>   
                dina_4 <= DataOut;
            when adres(4) =>   
                dina_5 <= DataOut;
            when adres(5) =>   
                dina_6 <= DataOut;
            when adres(6) =>   
                dina_7 <= DataOut;
            when adres(7) =>   
                dina_8 <= DataOut;
            when others =>
                dina_1 <= "0000000000000000";
                dina_2 <= "0000000000000000";
                dina_3 <= "0000000000000000";
                dina_4 <= "0000000000000000";
                dina_5 <= "0000000000000000";
                dina_6 <= "0000000000000000";
                dina_7 <= "0000000000000000";
                dina_8 <= "0000000000000000";
        end case;
        if indeks = 0 then
            indeks <= 1;
        else 
            indeks <= 0;
        end if;
        nr_adc  <= adres(indeks);
    end if;
  end if;
end process;

end Behavioral;

Best Regards,

Michael

jpeyron · December 17, 2018

Hi @donwazonesko,

Here is a description of Blockram vs. Distributed RAM. Here is a website using distributive ram in VHDL that should be helpful. Here is a project using bram in Verilog. Here is a XADC project in vhdl done for the basys 3 by a community member. Here is a link to our projects for the basys 3 on GitHub.

cheers,

Jon

donwazonesko · December 17, 2018

@jpeyron

Thanks a lot!

donwazonesko · December 18, 2018

Hello,

@jpeyron

I've read all of the examples in links that you've included and the most important one is the second one. However there is no line that increment the address value. How does it work? Does it increase the address with every rising edge or maybe it fulfill the whole 256 array with data? The code is from link.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ram_example is
port (Clk : in std_logic;
        address : in integer;
        we : in std_logic;
        data_i : in std_logic_vector(7 downto 0);
        data_o : out std_logic_vector(7 downto 0)
     );
end ram_example;

architecture Behavioral of ram_example is

--Declaration of type and signal of a 256 element RAM
--with each element being 8 bit wide.
type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
signal ram : ram_t := (others => (others => '0'));

begin

--process for read and write operation.
PROCESS(Clk)
BEGIN
    if(rising_edge(Clk)) then
        if(we='1') then
            ram(address) <= data_i;
        end if;
        data_o <= ram(address);
    end if; 
END PROCESS;

end Behavioral;

jpeyron · December 18, 2018

Hi @donwazonesko,

The address and increment looks to be done in the top file. Here is another link with more examples of bram. I would look at the verilog project linked above as a reference for the process of using the bram.

thank you,

Jon

donwazonesko · December 18, 2018

@jpeyron

I think this might help!

Since XADC in Basys3 works sequentially (i've chosen it to works this way) and it goes from 1 to 8 then i can increase memory addres by 1 after the last (xadc) adress check, and restart the value when it gets up to 4096.

Here's goes nothing:

-- in the architecture --
    signal adres_RAM        : integer := 0;

OutputBuffer: process(dclk_in)
    begin
      if(dclk_in'event and dclk_in = '1') then
        if(DataReady = '1') then       
            case nr_adc is
                when adres_pmod(0) =>   
                    dina_1 <= DataOut;
                when adres_pmod(1) =>   
                    dina_2 <= DataOut;
                when adres_pmod(2) =>   
                    dina_3 <= DataOut;
                when adres_pmod(3) =>   
                    dina_4 <= DataOut;
                when adres_pmod(4) =>   
                    dina_5 <= DataOut;
                when adres_pmod(5) =>   
                    dina_6 <= DataOut;
                when adres_pmod(6) =>   
                    dina_7 <= DataOut;
                when adres_pmod(7) =>   
                    dina_8 <= DataOut;
					adres_RAM <= adres_RAM +1;
                when others =>
                    dina_1 <= "0000000000000000";
                    dina_2 <= "0000000000000000";
                    dina_3 <= "0000000000000000";
                    dina_4 <= "0000000000000000";
                    dina_5 <= "0000000000000000";
                    dina_6 <= "0000000000000000";
                    dina_7 <= "0000000000000000";
                    dina_8 <= "0000000000000000";
            end case;
            if indeks = 0 then
                indeks <= 1;
            else 
                indeks <= 0;
            end if;
			if adres_RAM = 4096 then
				adres_RAM <= 0;
			end if;
            nr_adc  <= adres_pmod(indeks);
        end if;
      end if;
    end process;
    end Behavioral;

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