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Miakatt

Faint 7-seg display LEDs.

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Hi all,

I have the same symptoms as the OP posted here:

I have been following tutorials, implementing simple designs like Adders, Shift-Registers etc. All was going fine until today when I implemented a Counter. The synthesis, implementation and bitstream generation succeeded, albeit with some warnings. When I flashed the FPGA, the 'program complete' LED lights up, and the 7-segment display is faintly lit. 

The project doesn't use the 7-seg, it displays the count in binary on the LED above the switches. 

The Info at the end of the programming says:

INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.

During synthesis, I also get the warning:

[Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

... even though I have a valid .xdc constraints file. 

 

So I went back to my earlier (working) examples, and after loading on to the FPGA, they give the same results and are no longer working. 

I downloaded the Basys3 GPIO example from Digilent and loaded that, and everything works fine (phew! I haven't blown the FPGA after 1 week!)

 

All my internet searches bring me to a Xilinx page https://www.xilinx.com/support/answers/64764.html

but I don't have a dbg_hub in my netlist as explained in the solution. 

Can anyone please help? 
 

 

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Hi,

the debug core warning is harmless (it's simply not used for a simple RTL-only design).

Faintly lit LEDs are fairly common when unused pins are configured to soft pullup (or pulldown). Those pins are routed to one rail via ~10 kOhms internally, The resulting sub-milliampere current isn't enough to light the LED up, but it shows faintly.

I can't comment on that specific board. But in general, FPGAs tend to be extremely robust, as long as external voltages are limited to the the IO voltage range (0 V to 3.3 V, typically). Use common sense, but don't worry about the board. It's meant to be used, if it fails it fails and most likely there's not a thing you could have done to change that (other than putting it into a locked closet).

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" It's meant to be used, if it fails it fails and most likely there's not a thing you could have done to change that (other than putting it into a locked closet)."

Good advice! But the 7-segment LEDs didn't light up at all previously unless intended. So I tested one of the previous project that *does* use the 7-segment display, and that actually worked, with the unused segments fully off. So I think you're correct about the unused pins in my other projects causing the faint glow (although they didn't do that initially).

And strangely, (while I'm writing this), testing one of my other (non 7-segment display) projects, a USR, that is also now working. The LEDs are still faint. So I may add a feature in the code to shut them off. 

So, I'm still alive (well, my FPGA is) and it won't be going in to a locked cupboard! 

 

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Thanks xc6Ix45.

So, if I understand this correctly, with this command in the .xdc file,

set_property BITSTREAM.CONFIG.UNUSEDPIN <Pullup, Pulldown, Pullnone> [current design]

during bitstream generation and subsequent running, all unused pins will be put in to the desired state (pullup/pulldown/pullnone).

And it is safe to declare any of these options?

I'm just trying to get a feel of how/if the hardware can be damaged by rooky mistakes in the code. But, I'm also hoping VHDL wouldn't include such a command if it were so likely to do damage!

 

 

 

 

 

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