I have been following tutorials, implementing simple designs like Adders, Shift-Registers etc. All was going fine until today when I implemented a Counter. The synthesis, implementation and bitstream generation succeeded, albeit with some warnings. When I flashed the FPGA, the 'program complete' LED lights up, and the 7-segment display is faintly lit.
The project doesn't use the 7-seg, it displays the count in binary on the LED above the switches.
The Info at the end of the programming says:
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
During synthesis, I also get the warning:
[Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
... even though I have a valid .xdc constraints file.
So I went back to my earlier (working) examples, and after loading on to the FPGA, they give the same results and are no longer working.
I downloaded the Basys3 GPIO example from Digilent and loaded that, and everything works fine (phew! I haven't blown the FPGA after 1 week!)
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Miakatt
Hi all,
I have the same symptoms as the OP posted here:
I have been following tutorials, implementing simple designs like Adders, Shift-Registers etc. All was going fine until today when I implemented a Counter. The synthesis, implementation and bitstream generation succeeded, albeit with some warnings. When I flashed the FPGA, the 'program complete' LED lights up, and the 7-segment display is faintly lit.
The project doesn't use the 7-seg, it displays the count in binary on the LED above the switches.
The Info at the end of the programming says:
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
During synthesis, I also get the warning:
[Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
... even though I have a valid .xdc constraints file.
So I went back to my earlier (working) examples, and after loading on to the FPGA, they give the same results and are no longer working.
I downloaded the Basys3 GPIO example from Digilent and loaded that, and everything works fine (phew! I haven't blown the FPGA after 1 week!)
All my internet searches bring me to a Xilinx page https://www.xilinx.com/support/answers/64764.html
but I don't have a dbg_hub in my netlist as explained in the solution.
Can anyone please help?
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