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Hong

Vivado sysnthesis fail..Pcam

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error_msg.png.a90a5d3e0c644066299c74e230303cff.png

My Vivado Ver 18.3 and every time occured error like picture...

My board is Zybo Z7 20 + Pcam... I already did it all like forum solution.

Plz let me know how to solve it.

I did it below steps.

1. Download the latest version of the Pcam 5C Demo project from https://github.com/Digilent/Zybo-Z7-20-pcam-5c, in zip format.

2. Use the vivado library zip file (which includes the D-PHY and CSI-2 IPs) you previously downloaded from https://github.com/Digilent/vivado-library/tree/feature/d-phy, or download it again.

3. Unzip the two zip files, put the vivado library in its folder under the repo folder.

4. Run the create_project.tcl script from Vivado 2018.3.

5. In the project block diagram, double-click on the MIPI_CSI_2_RX_0 IP and deselect Debug Module. Press OK. Save the project.

6. HDL Wapper -> Generate Birsteam.

Always result is same, so I can't work anything..................

 

thanks

error_msg2.jpg

Edited by Hong

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Hi @Hong,

Thank you for bringing up this issue, unfortunately without a log file we don't actually know what's wrong with it because the message you have provided is a generic error message. Could you please provide the log file?

Taking in to account that 2018.3 is a very recent product (currently 4 days old) we have not yet updated our demo projects to this version. Differences between Vivado versions tend to come with changes which might make our demos fail. We usually recommend a specific Vivado version in our demo projects, if you go to Zybo-Z7-20-pcam-5c Demo you will notice that in the description of the project we specify "Created for Vivado 2017.4". We can guarantee that it will work in that version.

If you need it to work with 2018.3 you will have to wait for us to update our demo or try to update it yourself.

- Ciprian

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ERROR: [Synth 8-485] no port 'axis_data_count' on instance [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:578]
ERROR: [Synth 8-485] no port 'axis_data_count' on instance [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:578]
ERROR: [Synth 8-485] no port 'axis_data_count' on instance [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:111]
ERROR: [Synth 8-285] failed synthesizing module 'LLP' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:79]
ERROR: [Synth 8-285] failed synthesizing module 'MIPI_CSI2_Rx' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/MIPI_CSI2_Rx.vhd:77]
ERROR: [Synth 8-285] failed synthesizing module 'mipi_csi2_rx_top' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/MIPI_CSI2_RxTop.vhd:131]
ERROR: [Synth 8-285] failed synthesizing module 'system_MIPI_CSI_2_RX_0_0' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ip/system_MIPI_CSI_2_RX_0_0_1/synth/system_MIPI_CSI_2_RX_0_0.vhd:112]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 762.250 ; gain = 408.602
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
86 Infos, 123 Warnings, 0 Critical Warnings and 8 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Sat Dec 22 12:16:05 2018...

 

This is the part of log file....

What is the problem???

 

Plz let me know how to fix this error.......thanks

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Hi @JulianPeter,

I have reached out to @Ciprian as this thread has appeared to slipped through the cracks. We typically try to upgrade most of our project on the   xxxx.4 version of Vivado.  I am currently  unaware when/if the Zybo-Z7-PCAM-5C project will be updated.

thank you,

Jon

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Hi,

We are planning to update our project to 2018.3 but we don't have a precise release date for it yet. If it's not mandatory to use 2018.3 please stick with 2017.4 with this project for the time being.

-Ciprian

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The error is due to IPs and sub-IPs not being upgraded to the new version. I just posted a new release of the project which aligns the format with the digilent-vivado-scripts flow and upgrades everything to 2018.2. See here.

Notice anything amiss? Post on issue on GitHub.

It cannot be said often enough that Digilent only supports the Vivado version the project was released for. Furthermore, for a healthy dose of mental sanity, only one version is supported per year. For the year 2018 it is 2018.2, and not 2018.3 as @Ciprian said.

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I have used the new realease for 2018.2 but although I had errors, follwoing the guide in the README:

1. Timing errors, negative slacks:

imagen.thumb.png.e4f33a443801ea42c78747e85462e115.png

2. The make file error, it says it is not defined

3. It says that the platform has not been initialized. Everything happens as soon as importing the file systems in the sdk after creating the Application Project. Note also creating two application projects creates the crush of the program.

 

 

 

 

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Posted (edited)

@Esti.A,

1. The timing error is localized to the DPHY input. The Digilent MIPI D-PHY IP is functional, but not optimized. Feel free to replace it with Xilinx's offering.

image.png.b2282fd081d49200976a860847babf85.png

2. Just did a clean clone and re-did what the readme steps. Fixed the readme to ask for C++ instead of C, which I already told you in the issue you raised on Github. The workspace should look like this:

image.png.8f856e595097e0257865015067f86f32.png

3. There is little we can do about SDK application crashes.

Edited by elodg
Fixed screenshot duplication

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Hello Dear @elodg , @jpeyron , @Ciprian

I've downloaded PCAM demo from the link here as elodg provided and I also installed the Vivado version of 2018.2. Everything went good, and generated bitstream normally. After I launched SDK and I run the application "pcam_vdma_hdmi" or "fsbl", I cannot capture the video from the sensor. I am getting the attached errors. There is no HDMI output, no streaming to ILA core, and no tera term connection. What may be the problem?  

My best regardsSDK_Errors.thumb.png.ca631249d226d89b860f6251a7f3106c.pngNo_Connection_no_image.thumb.png.af0f0d8c3c8e2bedf820a726b0a253da.png

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Hi @Sduru,

I found a xilinx forum that that discusses this issue here. For their  project the .project and .cproject files were referencing an obsolete hw_platform that no longer existed. They manually edited the files to the new hw_platform--now the design worked.

Did you use the 2018.2 project from the release page here?

Did you import the fsbl and pcam_vdma_hdmi from the sdk_appsrc folder in the Zybo-Z7-20-Pcam-5C-2018.2.1 folder?

best regards,

Jon 

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Hello Dear @jpeyron

I've already solved the problem. It was related to selecting wrong language C instead of C++ when creating new application project. PCAM project was written in C++, but I wrongly selected C! After I corrected that mistake, now there is no any linking error.

Thanks... 

 

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Hi @Sduru,

Glad to hear that you resolved the issue. Thank you for sharing what you did to resolve the issue.

cheers,

Jon

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