My Vivado Ver 18.3 and every time occured error like picture...
My board is Zybo Z7 20 + Pcam... I already did it all like forum solution.
Plz let me know how to solve it.
I did it below steps.
1. Download the latest version of the Pcam 5C Demo project from https://github.com/Digilent/Zybo-Z7-20-pcam-5c, in zip format.
2. Use the vivado library zip file (which includes the D-PHY and CSI-2 IPs) you previously downloaded from https://github.com/Digilent/vivado-library/tree/feature/d-phy, or download it again.
3. Unzip the two zip files, put the vivado library in its folder under the repo folder.
4. Run the create_project.tcl script from Vivado 2018.3.
5. In the project block diagram, double-click on the MIPI_CSI_2_RX_0 IP and deselect Debug Module. Press OK. Save the project.
6. HDL Wapper -> Generate Birsteam.
Always result is same, so I can't work anything..................
Question
Hong
My Vivado Ver 18.3 and every time occured error like picture...
My board is Zybo Z7 20 + Pcam... I already did it all like forum solution.
Plz let me know how to solve it.
I did it below steps.
1. Download the latest version of the Pcam 5C Demo project from https://github.com/Digilent/Zybo-Z7-20-pcam-5c, in zip format.
2. Use the vivado library zip file (which includes the D-PHY and CSI-2 IPs) you previously downloaded from https://github.com/Digilent/vivado-library/tree/feature/d-phy, or download it again.
3. Unzip the two zip files, put the vivado library in its folder under the repo folder.
4. Run the create_project.tcl script from Vivado 2018.3.
5. In the project block diagram, double-click on the MIPI_CSI_2_RX_0 IP and deselect Debug Module. Press OK. Save the project.
6. HDL Wapper -> Generate Birsteam.
Always result is same, so I can't work anything..................
thanks
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