Nexys A7 Reference Manual: SDRAM - Mbps vs MBps

[tschaboo]

In the reference manual Table 3.3.1 it says

"Recommended clock period = 3077ps" and "650 Mbps data rate". I doubt this is correct. 1/3077 ps = 325 MHz. At a data width of 16 bits that's 2 Bytes per cycle. That would be 650 MBps. Actually, since it's DDR, shouldn't it be even twice that? 1300 MBps / 10.4 Gbps ?

[zygot]

The convention for external memory data rate is on a per pin basis so the reference manual is correct. The peak data rate out of the external memory, as you surmise, depends on the width of the physical memory. If you have a single port (channel) external memory controller then a more important metric is how many bytes/s can you get out of the controller into your FPGA design. If you have a multi port controller vying for access to the memory then the peak data rate out of the external memory becomes significant. There are a lot of moving parts to trying to figure out if an external memory implementation will support any particular application as you likely suspect. There are a lot of factors to consider such as maximum DDR data rates for a particular device, memory burst length, and controller verses data clock ratio.

[edit] I should also point out another possible source of confusion. Clearly the 650 Mbps refers to 'million bit per second'. Once you start talking about 'mega bytes per second' you'd be referring to million bytes per second divided by 1.048576. The hard disk drive manufacturers have been pulling our legs for some time by redefining the term megabyte to enhance the perceived capacity of it's products.

[jpeyron]

Hi @tschaboo,

The Nexys 4 DDR Resource Center will also be helpful. The resources were originally created for the Nexys 4 DDR board but should be useful to users of the Nexys A7, as the boards are nearly identical. Under the  additional resources on the Nexys 4 DDR resource center the SRAM to DDR Component  and the Nexys 4 DDR Xilinx MIG Project should be helpful.

thank you,

Jon