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julianop99

PMOD CAN with UltraZed

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Hi

I am trying to use 2 PMOD CAN transceivers with a Ultrazed-EG IOCC card. I have got the vivado library 2018.2, but the problem is that my card is not supported.

Is there a way of changing the vivado_library files so I can include my card and have the synthesis and bistream generated?

Best regards, 

julianop99

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Hi @Juliano Pimentel,

We currently do not have the bandwidth to alter the board files and Vivado library IP's to work with FPGA's not currently being used with our products. For the Pmod CAN IP Core i believe we altered the AXI_QUAD_SPI IP Core. You could configure the AXI_QUAD_SPI Ip Core to communicate with the Pmod CAN. At this point it should not be to difficult to make your own drivers using the Pmod CAN IP Core as a reference. Here is a forum thread that should be helpful with the process of making the Pmod IP core work with your board. 

thank you,

Jon  

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Hi @jpeyron, thanks for the quick turnaround. I am quite new with this platform, so you mean to add an IP in Vivado, AXI Quad SPI, and change it to  communicate it with the PMOD CAN.

Any hint how to connect he AXI QUAD SPI external connection (SPI_0) to communicate with the transceiver, please?

Best regards,

julianop99

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Hi @Juliano Pimentel,

Sorry for any confusion from my earlier post. You have 2 options. First option is to add the AXI_QUAD_SPI IP Core and configure  it to communicate with the Pmod CAN. At this point it should not be to difficult to make your own drivers using the Pmod CAN IP Core as a reference.

Second option is to open a project with a board selected from an already supported family (zynq, Artix-7), then add the IP to a BD, then edit in IP packager. Then go to the Compatibility Packaging step, "add family, check the "all families and parts" box and then to "review and package", repackage the IP. 

You should then be able to change the target board and add the IPs you upgraded. Once you have added the upgraded IP core to the block design you will right click on the pmod out of the ip core you are trying to use and select make external. Then after you have created a wrapper you will need to constrain the pmod out pin using the xdc for your board. m and export the hardware including the bitstream. Then launch sdk. Once sdk is open make a new application with the empty template. Then move the main.c file from the examples folder of the Pmod CAN drivers IP core( vivado-library/ip/Pmods/PmodCAN_v1_0/drivers/PmodCAN_v1_0/examples/) to the scr folder of the application. Then program the fpga and run the application.

Here is a forum thread that should be helpful with the second option of making the Pmod IP core work with your board.  

cheers,

Jon

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On ‎12‎/‎7‎/‎2018 at 4:21 PM, jpeyron said:

Hi @Juliano Pimentel,

Sorry for any confusion from my earlier post. You have 2 options. First option is to add the AXI_QUAD_SPI IP Core and configure  it to communicate with the Pmod CAN. At this point it should not be to difficult to make your own drivers using the Pmod CAN IP Core as a reference.

Second option is to open a project with a board selected from an already supported family (zynq, Artix-7), then add the IP to a BD, then edit in IP packager. Then go to the Compatibility Packaging step, "add family, check the "all families and parts" box and then to "review and package", repackage the IP. 

You should then be able to change the target board and add the IPs you upgraded. Once you have added the upgraded IP core to the block design you will right click on the pmod out of the ip core you are trying to use and select make external. Then after you have created a wrapper you will need to constrain the pmod out pin using the xdc for your board. m and export the hardware including the bitstream. Then launch sdk. Once sdk is open make a new application with the empty template. Then move the main.c file from the examples folder of the Pmod CAN drivers IP core( vivado-library/ip/Pmods/PmodCAN_v1_0/drivers/PmodCAN_v1_0/examples/) to the scr folder of the application. Then program the fpga and run the application.

Here is a forum thread that should be helpful with the second option of making the Pmod IP core work with your board.  

cheers,

Jon

Hi Jon. Thanks for the detailed instructions. I have managed to make CAN connection with the first option. Will also look into the second one. Many thanks, Juliano

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Hi @jpeyron, I am coming back to the 2nd half of your proposal above and have a few questions:

I believe I have managed to repackage the IP. Will give a try and let you know.

Best regards,

Juliano

Edited by Juliano Pimentel

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18 hours ago, Juliano Pimentel said:

Hi @jpeyron, I am coming back to the 2nd half of your proposal above and have a few questions:

I believe I have managed to repackage the IP. Will give a try and let you know.

Best regards,

Juliano

@jpeyron, sorry to bother you, but now my issue is with the bitstream generation. I need to route the PmodCAN Pmod_out signals to a PMOD at my Ultrazed board. I will use jx2_je_pmod at the board, for instance, but the bitgen is complying that I have not specified and constrained the ports.

Which pins from the Pmod_out at the PmodCAN IP should I specify, please?

Best regards

Juliano

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Hi @Juliano Pimentel,

In the block design you should expand the pmod out bus and right click on the T pins. I believe they are  1-4 and 7-10 and select make external.   Usually i will delete the wrapper and re-create the wrapper after i have updated the hierarchy.  Then I open the wrapper and create and XDC file. Next in the XDC I constrain the pins i wish to use with the T pmod out pin names in the wrapper. Make sure the lines are uncommented in the XDC. Save the XDC file and generate a bitstream. If you are still having issues generating a bitstream please attach screen shots of how you have connected the pins to the Pmod out of the Pmod CAN IP core, in the vivado block design as well as attaching the wrapper and xdc files.

thank you,

Jon

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Hi @Juliano Pimentel,

I have included screen shots of what I was describing using a Zedboard(Zynq) and the PmodCAN making the T pins external. The wrapper names for the T Pins are used in the XDC to constrain the JA Pmod Port Pins of the Zedboard. 

thank you,

Jon

PmodCAN_T_PINS_2.jpg

PmodCAN_T_PINS_1.jpg

PmodCAN_T_PINS_4.jpg

PmodCAN_T_PINS_3.jpg

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14 hours ago, jpeyron said:

Hi @Juliano Pimentel,

I have included screen shots of what I was describing using a Zedboard(Zynq) and the PmodCAN making the T pins external. The wrapper names for the T Pins are used in the XDC to constrain the JA Pmod Port Pins of the Zedboard. 

thank you,

Jon

PmodCAN_T_PINS_2.jpg

PmodCAN_T_PINS_1.jpg

PmodCAN_T_PINS_4.jpg

PmodCAN_T_PINS_3.jpg

Hi @jpeyron, thanks for that.  I have implemented the same BD as yourself, but it complains about the _i pins. Please see my printscreen.

I would appreciate your comments. Best regards.

 

image.thumb.png.868808e538aba3e2a2576ddb8ee89a6f.png

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