cmod-A7 SPI-bootloader starts with second connection

[Weevil]

Hi all,

i did the tutorial "How To Store Your SDK Project in SPI Flash" (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start) and everything works fine. 

...But now i recognise when, i connect the Cmod-A7 to my USB-port, the FPGA is programmed but the bootloader does not start the C-programm i created in the SDK. If i now disconnect and connect it again, the bootloader starts the C-programm and everything works fine. Maybe someone know how to handle this? 

[jpeyron]

Hi @Weevil,

Here is a forum thread that should help for your situation.

thank you,

Jon

[jpeyron]

Hi @Weevil,

I have not implemented a software reset in FPGA's before. Here is a forum thread that might be helpful for your situation.Another solution once you have programmed the QSPI you could then program the JTAG. To do this select the  program the fpga and changing the microblaze from the srec path back to bootloop. Then program the FPGA. Next right click on the application and run as-> launch on Hardware(System debugger). The normal process to loading the project onto the fpga from SDK.

cheers,

Jon

[Weevil]

Hi @jpeyron,

programming with JTAG and -> launch on Hardware(System debugger) works fine, but i would need to start the program when the board gets power on.

Actual the FPGA is programed by the SPI-flash on startup (control with a led). The problem is, the bootloader is sometimes not started. Is there a possbibility to adjust the startup sequence or can something else cause such error? 

...if i manual program the FPGA with the bootloader.elf it runs every time without problems and the bootloader is loading the program from the spi-flash...

Thanks you for your help! Greetings.

 

[jpeyron]

Hi @Weevil,

Try adding a delay in the beginning of your  SDK code. If you have compressed the bitstream and commented out verbose in the bootloader adding a delay can ensure that all of the rails are fully powered up before the application tries running.

thank you,

Jon

[Weevil]

Hi @jpeyron Jon,

i tryed a delay of 500ms in my SDK code similar as @BYTEMAN suggested in the post (https://forum.digilentinc.com/topic/9532-cmod-a7-35t-quad-spi-memory-question-and-peripheral-interfacing/). The difference in my code is the delay is before the while loop:

int main()
{
  MB_Sleep(500);
  
  while(1)
  {
    //do some stuff
  }
}

With this i still have the problem. As you suggested i use compressed bitstream and commented out verbose. For a test i tryed with verbose (it does not effect the problem) and got the position where the bootloader fails.

Sometimes it works and its looking like this:

Greetings, Weevil

[jpeyron]

Hi @Weevil,

Try adding the delay in the bootloader.

thank you,

Jon

[Weevil]

Hi @jpeyron

i did, nothing changed...

[Weevil]

Hi @jpeyron,

thank you so much!!! Its starting up save now.

 

I changed the following settings in my project:

- Set SPI Mode to "Standard"

- Select configuration mode "Master SPI x1"

Cheers, Weevil

[LucAce]

@Weevil, @jpeyron

Is there an explanation why this works?  The fetching of microblaze code from QSPI occurs long after the FPGA is configured and has released the QSPI interface.  So I don't see why this would change the ability of the bootloader to read flash.

I have been fighting this board for more hours then I would like to admit to, I have encountered multiple flash program failures or it just not being able to find the flash when the boot load starts trying to execute it.  The best I have gotten is to this point where the FPGA will run the microblaze code after the button is pressed/reset issued.

These are the properties I'm using when it requires a button press to being fetching from QSPI.

    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
    set_property CONFIG_MODE SPIx4 [current_design]

I have only tried using the USB interface. Using Debug builds in SDK, Verbose is defined (enabled) in the bootloader.