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Pavel_47

Adept software Manual ... looking for author

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Hello,

Is there some way to contact author of Digilent Adept JTAG Interface (DJTG) Programmer’s Reference Manual ?

This manual is literally unusable: crucial lack of information in virtually every chapter ... the author introduces a new concept (e.g. Batch Operation) and doesn't explain how it can be used !

Incredible !

Thanks.

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@Pavel_47,

I've noticed a few of your recent posts and understand your frustration. Might I suggest that the Adept software isn't the only possible approach to using the USB resources. I've used the FTDI driver APIs with the Nexys Video and there's a very recent project posted to the Project Vault that's an excellent tutorial for doing what you appear to be interested in for the CMOD.

Before venturing into specifics related to any USB device or API you have to have to have a good understanding of USB concepts and protocol. There are other resources for that.

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Hello Zygot,

Probably I was misunderstood.

I'm not interested in USB aspects of JTAG-SMT2™ module. I consider that the instruction I send over USB cable are properly translated in sequences on JTAG lines.

And it's JTAG aspect that I'm interested in. Unfortunately I didn't find any other approach to communicated with FPGA over JTAG.

Well ... there is some Tcl instructions in Vivado and SDK, but it's even worth ... while Digilent provide some documentation on Adept software with a couple of examples, Xilinx doesn't provide any examples.

Sincerely,

Pavel.

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3 hours ago, Pavel_47 said:

Probably I was misunderstood.

Hi @Pavel_47,

I'm afraid that I still don't understand what your goals are. If you are interested in configuring FPGA devices Xilinx device documentation is excellent and there are application notes and a few demonstration projects. If you want to pass data between a configured device and a PC xc6lx45 recently posted a project showing how to do that using the BSCAN primitive. I can't think of other uses for JTAG. Designing a boundary scan system to do say, a complete PCB test, will require a bit more research. There is an open source JTAG effort that might be instructive. IEEE 1149 covers boundary scan.

Edited by zygot

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12 hours ago, zygot said:

Hi @Pavel_47,

I'm afraid that I still don't understand what your goals are.

Hi Zygot,

The goal is to perform "customized" configuring of FPGA ... e.g. frame-based.

It means one frame or several frames (not whole bitstream !) are read, then modified in certain way, and then rewritten back in the FPGA.

To my knowledge there is no tools that provide such capability.

Sincerely.

Pavel.

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Hello Pavel,

I think you may be trying to carry out a partial FPGA re-configuration. I was doing this some time ago,, so cant remember exact details.. I guess it was maybe 7 years ago with ISE, and I did a little bit of this with Vivado a couple of years ago, but the recent stuff was mainly to do with configuring a small part of the FPGA (then activating it) to meet critical system interface timing demands, I guess that was partial configuration rather than partial re-configuration 🙂 .

Funny how we go from, re-configure to save silicone to pre-configure to save time eh Pavel 🙂

Perhaps a good place to look is search the Xilinx site for "Partial reconfiguration controller" I recall using it and I think there a a number of tools,  all Xilinx IP..

Hope that helps Gra

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@Pavel_47 ,

I have no experience doing what you intend to do but I suggest trying the Xilinx community forums. Intel also has a similar venue. I figure that having access to the largest set of eyes is the best chance of connecting with someone who has helpful information.

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Hi Gra,

Thanks for feedback. No, partial configuration isn't my primer interest, but rather ... as I sayed below - frame-based configuration, which is not the same thing.

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1 minute ago, zygot said:

@Pavel_47 ,

I have no experience doing what you intend to do but I suggest trying the Xilinx community forums. Intel also has a similar venue. I figure that having access to the largest set of eyes is the best chance of connecting with someone who has helpful information.

Thanks for suggestion Zygot. Xilinx forum as well as Xilinx official support were already tried ... no any result, so I should search for a solution myself.

Sincerely

Pavel

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