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CAN Data in PL


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Hi everyone

Hope everything is going well.

I want to communicate with can bus in PL as a master (in a real time system).

In Micro-Controllers, there are functions and classes that control the CAN Bus as a master or slave and provide required data.

Is there any detailed instruction to communicate with can bus in PL trough connecting to the CAN BUS Controller in PS? (AXI connections to CAN Controller Unit & ...)

 

 

Edited by CodeMagics
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Hi CodeMagics,

Let me try to answer your questions.

1. Unless you require extremely low latency the PS can be suitable for real time. You just need to operate it in a standalone (or bare metal) mode.

2. To my knowledge CABbus does not have master-slave relationship between nodes. The user can define such by programming the messages' ID. Otherwise all nodes can send messages at any time.

3. Due to its complexity CAN bus requires substantial code overhead. To my knowledge there is no open source VHDL or Verilog library supporting CAN. However, there are plenty of IP for microcontrollers. Xilinx offers free IP for Zynq PS as well. You can find it in Vivado SDK, for example, in the folder Xilinx\SDK\2018.1\data\embeddedsw\XilinxProcessorIPLib\drivers\canps_v2_1

Since Zynq PS is equipped with two CAN controllers the only thing you would need is a PHY module, for example, SN65HVD230 CAN breakout board. Digilent offers CAN Pmod as well, however, it uses a chip with CAN controller which is redundant in that case. It is however, useful when you need to use FPGA board without the ARM core.

I would recommend searching Digilent forums.

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