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Place design Error-Rule Violation[23-20] in Vivado


Question

I am getting the below error during implementation in AVENT Kintex Ultra scale (ku040) as per the data sheet. All the DDR pin specifications and I/O standards have checked and its correct but even its displaying below error message.

[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
[DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 45. For example, the following two ports in this bank have conflicting VCCOs:  
ddr4_sdram_dqs_t[2] (DIFF_POD12_DCI, requiring VCCO=1.200) and gt_reset (LVCMOS18, requiring VCCO=1.800)

Please anyone guide me.

Edited by Thausikan
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Hi,

this is just a general comment (I don't own the board, maybe someone else is more familiar with this particular issue):

First, KU040 is the name of a chip, not a board. I assume you are referring to this one (manual).
If so, bank 45 for DDR is supplied by 1.2 V.

Apparently, the "gt_reset" pin in your toplevel design wants to drive 1.8 V. This is physically impossible (one bank has only a single positive rail voltage).

Possible solutions:

  • change the IO voltage of gt_reset to 1.2 V. For the above-mentioned board, Push_SW[0:4], DIP_SW[0:7] on bank 45 should be driven by 1.2 V on the other end of the switch, if the board is designed correctly.
  • double-check that gt_reset is an input (AFAIK, mixing IO voltages is OK for pins that are input-only)
  • or move gt_reset to a different bank that is supplied by 1.8 V

 

 

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