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About the specification of NexysVideo


koseki

Question

Please forgive immature English

Hello
I am developing a project of image processing on the NexysVideo board
And it is completed and it works well at 1920 x 1080 p 60 Hz

Recently I bought a new NexysVideo board
And I programmed the same project but there is a problem with the operation
※ "Symptoms similar to" Defective pixel "and" Moire "appear (see attached image)

I have a question
Are there any specifications differences between NexysVideo board specifications this spring (2018/04) and the latest (2018/11)?
Or is it exactly the same?

Thank you

1543280771138.jpg

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Hi @koseki,

There has not been a change in the Nexys Video development board anywhere close to the two times you stated. Whenever we experience  visual artifacts the first thing we do is check the cable connections and then re-load the project. What type of image processing are you working on?

thank you,

Jon 

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Hello, @ jpeyron
Thank you for your reply.

Thank you for investigating!

I am sorry, I can not describe the detail of image processing ....
It inputs images, performs arithmetic processing on all pixels, and outputs images in real time. And occupies much of the FPGA resources.

However, this phenomenon also occurs on the function of HDMI passthrough. it's incomprehensible.

I think I will investigate cable connection and whether there is a place inside the project that is bad.

Thank you.

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Hi, jpeyron
Thank you for your reply.

This HDMI design was designed using dvi2rgb (1.9), rgb2dvi (1.4), ClockingWizard (6.0) with reference to Nexys Video User Demo.

I also contacted AVNET x-hotline. The answer is,
「1920 x 1080 The pixel clock (148.5 MHz) operation of 60 p requires 742.5 MHz for IO, but the upper limit of BUFIO of Artix chip is 680 MHz.
Since it exceeds the upper limit, 1920 x 1080 60p can not be guaranteed because there are things that do not work and those that work depending on individual differences and environments in operation.
If you drop fps to 30 or design it with HDMI using GT, it will solve it.」

I would like to try HDMI design using GT.

Are dvi 2 rgb and rgb 2 dvi correct on HDMI IP using IO?
Also, do you have digient for HDMI IP that uses GT?

Thank you.

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Funny, I'm having the same issue with the Nexys video, dvi2rgb(1.7) out of the demo. having the same artifacts at 60fps. And I appreciate every development in your work!

BTW: The artifacts disappear when plugging in and out hdmi several times.

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Hi @koseki,

The HDMI is wired to bank 34 of the FPGA as shown in the Nexys Video schematic on page 11.  The  transceivers are routed to the Display Port and the FMC on bank 216 on page 11. Here and here are forum threads talking about using the Display Port if you were wanting to use the GTX lanes of the Display port. Here is rgb2dpvid user guide that appears to be for the Display port.

cheers,

Jon

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I think the problem is not the HDMI output but the HDMI input. So changing to DP-out will not give a better result. I am Using the dvi2rgb directly with a LVDS lane directly to the Display (at the moment just pass through) and the errors occur. There are timing issues in the intraclock path: clk_out_5x_hdmi_clk :  dvi2rgb_inst/DataDecoders[x].DecoderX/InputSERDES_X/DeserializerMaster/CLK and CLKB. Required: 1.667ns pulsewidth. actual pulse width: 1.347 (5xPixclk). I assume that's the reason for this error. But the SERDES_X is just for 600MHz and not the required 750MHz. So obviously the Nexys Video cannot be used for a FullHD60FPS stream...

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Hi,

The design of HDMI using GT takes a little time.
I decided to lower fps to 30 first.

I tried it with a simple HDMI design to isolate the problem. But the result did not change.
I think that fps has fallen and timing problems are gone.
But the screen got stained red.


Is there anything wrong with my setting?

Thank you.

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image.png.5fef8ac95e815f4aeb6f3f7306623e8a.png

image.png.22cb357bb69ac95c852e949aeb76538d.png

## Clock Signal
set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports sys_clock]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock]

## HDMI in
set_property -dict {PACKAGE_PIN W4 IOSTANDARD TMDS_33} [get_ports hdmi_rx_clk_n]
set_property -dict {PACKAGE_PIN V4 IOSTANDARD TMDS_33} [get_ports hdmi_rx_clk_p]
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_hpa]
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_ddc_scl_io]
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_ddc_sda_io]
set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_txen]
set_property -dict {PACKAGE_PIN AA3 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_n[0]}]
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_p[0]}]
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_n[1]}]
set_property -dict {PACKAGE_PIN W2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_p[1]}]
set_property -dict {PACKAGE_PIN V2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_n[2]}]
set_property -dict {PACKAGE_PIN U2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_p[2]}]

## HDMI out
set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports hdmi_tx_clk_n]
set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports hdmi_tx_clk_p]
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_n[0]}]
set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_p[0]}]
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_n[1]}]
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_p[1]}]
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_n[2]}]
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_p[2]}]

## HDMI clock
create_clock -period 13.468 [get_ports hdmi_rx_clk_p]
create_clock -period 13.468 [get_ports TMDS_Clk_p]
create_clock -period 13.468 [get_ports PixelClk]

image.png.38055781bfb8ebbbd47bfde18130e8d7.png

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