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CORA Z7-10 SDA SCL Lines remains LOW upon programming FPGA


Go to solution Solved by jpeyron,

Question

Hello,

I am using cora z7-10 to communicate with IMU using i2c protocol. So i am using i2c peripherals available in zynq itself and routed through EMIO to SDA and SCL pins available on board(P15 and P16 respectively). In constrained file i have pulled up both the pins . Also i have pulled up both the lines using 1k resistor externally.  But as soon as i program the fpga, both the lines goes LOW from HIGH and stays low. I dont see any clock pulses on SCL line too.

Why i dont see any pulses on scl line? Ideally both the lines should have been remain high after programming FPGA right?

Thank you

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