CORA Z7-10 SDA SCL Lines remains LOW upon programming FPGA

[Creative]

Hello,

I am using cora z7-10 to communicate with IMU using i2c protocol. So i am using i2c peripherals available in zynq itself and routed through EMIO to SDA and SCL pins available on board(P15 and P16 respectively). In constrained file i have pulled up both the pins . Also i have pulled up both the lines using 1k resistor externally.  But as soon as i program the fpga, both the lines goes LOW from HIGH and stays low. I dont see any clock pulses on SCL line too.

Why i dont see any pulses on scl line? Ideally both the lines should have been remain high after programming FPGA right?

Thank you

[jpeyron]

Hi @Creative,

Here is a forum post that describes the process of getting the I2C going through the EMIO pins on a ZYNQ board. This thread should help with your project.

cheers,

Jon