Problem with flashing board(arty z7) on specific project

[worm]

I have problem with program my z7-20 board. right after flashing, board resets and program is no continued. Vivado give me error "[Labtools 27-3165] End of startup status: LOW". If i change loop to shorter value(e.g. 0 to 9) it works. but i want to set it for example 80 and do it on single cycle. It is possible for this board?

vhdl file and constrains are in attachement.

 

mainvhdl.vhdl

maincons.xdc

[jpeyron]

Hi @worm,

The QSPI Flash is connected directly to the ZYNQ processor. To program the flash on a zynq board you will need to do this from SDK. Here is an older tutorial that is for a different ZYNQ board but should work just fine for your needs.

thank you,

Jon

 

 

 

[worm]

22 hours ago, jpeyron said:

Hi @worm,

The QSPI Flash is connected directly to the ZYNQ processor. To program the flash on a zynq board you will need to do this from SDK. Here is an older tutorial that is for a different ZYNQ board but should work just fine for your needs.

thank you,

Jon

thanks but after flash on qspi my program is still reseting board(now is reseting non stop). I think there is another reason. Maybe you have not understood me. flashing my board works properly when i have loop from 0 to 9, but no when 0 to 80(or even 50) 

[jpeyron]

Hi @worm,

To clarify you are configuring the QSPI with your VHDL code using a boot.bin and loading the project into the QSPI in SDK? Once this is done the project will work fine if it is set to only loop 10 time. The project does not work if the loop is set to run more than 10 times. Have you verified that this project works as intended configuring the project into the board by JTAG?

cheers,

Jon

[worm]

On 11/28/2018 at 12:14 AM, jpeyron said:

Hi @worm,

To clarify you are configuring the QSPI with your VHDL code using a boot.bin and loading the project into the QSPI in SDK? Once this is done the project will work fine if it is set to only loop 10 time. The project does not work if the loop is set to run more than 10 times. Have you verified that this project works as intended configuring the project into the board by JTAG?

cheers,

Jon

For sure, after flashing(using boot.bin) when loop have range 0 to 79, all diodes are blinking(device restarting for sure). when i make boot.bin with loop 0 to 9 diode(led4_r) red is on so works perfectly. TNS is below -10000ns it can be reason? Any idea? 

 

Working: 

Not working:

 

[jpeyron]

Hi @worm,

Could you add a delay in to the beginning of the project you are loading into the QSPI. This might be an issue of the board not being fully powered on.  Could you try loading this HDL Arty-Z7-20 xadc project here into qspi?

thank you,

Jon

[worm]

18 hours ago, jpeyron said:

Hi @worm,

Could you add a delay in to the beginning of the project you are loading into the QSPI. This might be an issue of the board not being fully powered on.  Could you try loading this HDL Arty-Z7-20 xadc project here into qspi?

thank you,

Jon

Xadc project:

My project delay 5s

Regards

[jpeyron]

Hi @worm,

First off, the xadc project loaded into the QSPI appears two be working without an issue. I would guess the issue can be resolved in the your HDL project. The delay added to your project seems to be part of the loop. Please post the VHDL code you are using with the delay included. Could you try again but add the delay prior to the loop.

thank you,

Jon  

[worm]

38 minutes ago, jpeyron said:

Hi @worm,

First off, the xadc project loaded into the QSPI appears two be working without an issue. I would guess the issue can be resolved in the your HDL project. The delay added to your project seems to be part of the loop. Please post the VHDL code you are using with the delay included. Could you try again but add the delay prior to the loop.

thank you,

Jon  

thanks for reply, sending code in attachment. Loop is starting after 5 sencods. 

Regards.

delay loop.vhdl

[jpeyron]

Hi @worm,

I can not see the issue with the VHDL but i would guess is that its the implementation of the SHA-1 HASH Algorithm. Are you able to get the VHDL to work correctly without trying to use the qspi?

thank you,

Jon

[worm]

8 minutes ago, jpeyron said:

Hi @worm,

I can not see the issue with the VHDL but i would guess is that its the implementation of the SHA-1 HASH Algorithm. Are you able to get the VHDL to work correctly without trying to use the qspi?

thank you,

Jon

yes it is sha1, without qspi it work the same. I dont want to use it on few clock cycles like it is in multiple examples but on single cycle. I wonder now if it is possible on this device at all.

[jpeyron]

Hi @worm,

I do not have experience with using the SHA1 algorithm. I haven't found any information about using the SHA1 algorithm a zynq development board. I would suggest to reach out to xilinx support as well.

thank you,

Jon 

[worm]

12 hours ago, jpeyron said:

Hi @worm,

I do not have experience with using the SHA1 algorithm. I haven't found any information about using the SHA1 algorithm a zynq development board. I would suggest to reach out to xilinx support as well.

thank you,

Jon 

ok thanks.

[xc6lx45]

On 11/28/2018 at 11:33 PM, worm said:

TNS is below -10000ns it can be reason? Any idea?  

Yes, most likely this is the reason: Your design fails timing and does not work. Please don't assume that small amounts of TNS fail "soft" (but don't assume either that functional failure is guaranteed). The attempt to P&R an impossible design may wreck other parts that would have been uncritical otherwise.

You're trying to run SHA1 in a single clock cycle. This is very inefficient use of the FPGA.

I haven't tried this example myself but I believe you can let register rebalancing do the work to turn it into a feasible design if you simply delay the output by e.g. 100 clock cycles via a shift register. It should be available in the options, if it isn't already enabled by default.

Done correctly, you can have many independent calculations in flight at the same time ("pipelined") and get much better overall performance from the FPGA logic.