Using XADC and GPIO on Zybo

[Mehdim]

Hello everybody,

I have some issue regarding using XADC and GPIO on Zybo board. Here is the situation:

When I use just GPIO, everything works fine and proper.

Also when I used XADC alone everything works good.

But when I use both GPIO and XADC, I get some error in generating bit-stream which shows that incompatible IO bank because of nature of “GPIO” and A/D converter.

 

Here is my block-diagram:

and here is the error message.

do you guys have any idea or experience regarding this issue?

thank you in advance.

[JColvin]

Hi Mehdim,

I have asked some of our applications engineers about this; they will get back to you here on the Forum.

Thanks,
JColvin

[TommyK]

Hi Mehdim,

It looks like your XADC pins are constrained to use IOSTANDARD LVCMOS18, which should be LVCMOS33. You need to find out where you are constraining the Vp_Vn and Vaux14_p/n pins and change it. This should be a .xdc file in your sources.

The reason it works when you use XADC alone is that the synthesizer doesn't see a VCC conflict with other pins on the FPGA bank. It will assume the whole bank is 1.8V and synthesize, even though the bank is still 3.3v.

[Mehdim]

Hello Tom,

Thanks for the prompt reply. Actually I have not added any constraint file to my design. As you see in the picture there is no such XDC file in project.

Do you mean some manipulating some constraint file that Vivado automatically generate?

[Mehdim]

I have find some XDF file  as you see below

 

 

And added some constraint regarding N15 and N16( right now I am using AD14 which is connected to N15 and N15 due to datasheet)

 

#

set_property iostandard "LVCMOS33"

set_property PACKAGE_PIN "N15"

set_property slew "slow"

set_property drive "8"

 

 

# 

set_property iostandard "LVCMOS33"

set_property PACKAGE_PIN "N16"

set_property slew "slow"

set_property drive "8"

 

but still it does not work

[TommyK]

Alright, how did you generate your block design? I'm curious where the Vaux14 interface came from. Did you just right click and make it external? Try right clicking in your design sources and "Add Sources...". Then select "Add or create constraints" and click next. Then create file, name it whatever, and click finish. This will make a constraints file (.xdc) in your design sources under the Constraints folder. Open that file and copy and paste the following lines:

set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { vauxp14 }];
set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { vauxn14 }];

[TommyK]

Also be sure to constrain the Vp_Vn interface with whatever pins it is using.

[Mehdim]

Thnaks Tom,

I design diagram based on adding needed IP cores and use connection automation for interconnect.

For Vaux14 , I jisy right clocked and used “create interface port”. I have did the steps as you said I think the problem is solved.

 

I have some other question regarding this issue, right now I have dedicated two single port for it as you see in the picture and it works fine with your mentioned constraint.

 

But if I use 2bit bus, as you see in the below picture, I again encounter the level issue. Is there any hint or trick for it?

[TommyK]

In the case of the bus, I'm pretty sure the pins are called "Vaux14_v_p" and "Vaux14_v_n". So change those in your xdc and it should work.

[Mehdim]

Great help Tom, Appreciate

[TommyK]

No problem! Glad I could help