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aramosam

Reprogram (reset) FPGA

Question

Hello all,

I have a Nexys4 DDR and I want to reprogram it, as it's done with "PROG" button.

As example I want to connect the IPROG/Program_B signal to be triggered when something happens like the output of my circuit is "1", or using a switch.

How can I do that? I've read documentation about multiboot but I don't want to load two bitstreams, only one and reprogram the FPGA with it when I want. I suppose that using the Program_b signal is the way to go but I don't know how I can use it.

Some code, tutorial or documentation would be appreciated.

Thank you

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Hi Alexis,

Unfoortunately, the program_b pin is only tied to the PROG button, and not to the FPGA. You can drive it with a Pmod port very easily though. Just take a wire and stick it under one of the bottom two feet on the PROG button. Put the other end into a Pmod port. In your .XDC file for your project, add a pullup to the port.

set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33  PULLUP TRUE} [get_ports { ja1 }];

Now you just pull ja1 low when you want to reprogram through QSPI. Make sure JP1 is on QSPI.

 

IMG_1601.JPG

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Hi Aramosam,

As described in the Nexys4 DDR reference manual under FPGA Configuration (section 3.1), there are four main ways to program and reset the board, the first being writing from a PC, the latter three all being from some attached memory. As I see it, there would be two main ways to accomplish what you're asking. First would be to write some kind of script on your PC to call Vivado to reprogram the FPGA when a certain UART signal is received, with the programming jumpers configured for the FPGA to be programmed from the USB-JTAG port. The second would be to wire the PROG button into a PMOD port, with the programming jumpers configured for the FPGA to be programmed from QSPI, USB HID, or the SD slot (I do not suggest actually doing this, as I have no idea what would happen, presumably the PMOD would go to zero once the board started being reprogrammed, but probably shouldn't assume). The former seems much safer, and this thread seems like a decent enough place to start https://forums.xilinx.com/t5/Archived-ISE-issues-Archived/Script-to-program-FPGAs/td-p/6074.

Thanks, Arthur

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12 hours ago, artvvb said:

Hi Aramosam,

As described in the Nexys4 DDR reference manual under FPGA Configuration (section 3.1), there are four main ways to program and reset the board, the first being writing from a PC, the latter three all being from some attached memory. As I see it, there would be two main ways to accomplish what you're asking. First would be to write some kind of script on your PC to call Vivado to reprogram the FPGA when a certain UART signal is received, with the programming jumpers configured for the FPGA to be programmed from the USB-JTAG port. The second would be to wire the PROG button into a PMOD port, with the programming jumpers configured for the FPGA to be programmed from QSPI, USB HID, or the SD slot (I do not suggest actually doing this, as I have no idea what would happen, presumably the PMOD would go to zero once the board started being reprogrammed, but probably shouldn't assume). The former seems much safer, and this thread seems like a decent enough place to start https://forums.xilinx.com/t5/Archived-ISE-issues-Archived/Script-to-program-FPGAs/td-p/6074.

Thanks, Arthur

Thank you for your answer Arthur,

The script seems an option. Unfortunately, in my case, I must reprogram the FPGA with the .bin in the QSPI because I'm going to perform a fault injection campaign and the board is going to be reprogramed a lot of times. Reprograming with Vivado takes a lot more time tan QSPI, and because this operation is going to be performed several times, the experiment could take too much time in finishing (we are talking about weeks).

 

Thanks, Alexis

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Actually, resetting/reprogramming the FPGA from within the internal logic of the FPGA isn't as hard as it sounds--once you figure out how to do it.  Check out the project wbicapetwo at opencores.  On there you'll see a core that can be used to access the internal ICAPE2 port within a series 7 FPGA.  I use it on my Basys-3 board (w/ Artix 7 FPGA) to reset the board from internal logic.  All it takes is to write a 15 (IPROG) to the command address, 0x04.  The FPGA will then reload its configuration.  Should you wish to load an alternate configuration, load the address of that alternate configuration on your flash into the WBSTAR register, found at address 0x010, and then issue the IPROG command.  You can find further documentation from Xilinx.  However, Xilinx's manual is sparse on the timing of this operation, and the core at opencores resolves that.

[email protected]

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On ‎09‎/‎03‎/‎2016 at 0:15 AM, tom21091 said:

Hi Alexis,

Unfoortunately, the program_b pin is only tied to the PROG button, and not to the FPGA. You can drive it with a Pmod port very easily though. Just take a wire and stick it under one of the bottom two feet on the PROG button. Put the other end into a Pmod port. In your .XDC file for your project, add a pullup to the port.

set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33  PULLUP TRUE} [get_ports { ja1 }];

Now you just pull ja1 low when you want to reprogram through QSPI. Make sure JP1 is on QSPI.

 

IMG_1601.JPG

So finally I've tried this solution and worked perfect. Be aware that the reprogram it’s going to be triggered when the output signal is 0. In my case (inside Vivado I made the following statement):

reprogram_output <= NOT reprogram_circuit_signal

 

 

 

On ‎10‎/‎03‎/‎2016 at 2:32 PM, [email protected] said:

Hi Alexis,

Unfoortunately, the program_b pin is only tied to the PROG button, and not to the FPGA. You can drive it with a Pmod port very easily though. Just take a wire and stick it under one of the bottom two feet on the PROG button. Put the other end into a Pmod port. In your .XDC file for your project, add a pullup to the port.

set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33  PULLUP TRUE} [get_ports { ja1 }];

Now you just pull ja1 low when you want to reprogram through QSPI. Make sure JP1 is on QSPI.

 

IMG_1601.JPG

While I’m performing my experiments with the other solution, I’m trying to implement this solution in order to release a “non wired” solution.

 

Thank you all for your answers.

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