Matthew Cabral

Question Regarding FPGA developement board for Senior Design Project

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Good Morning,

My name is Matthew and I am working on a senior design project where we need to make side scan sonar electronics to go along with a side scan sonar transducer provided to us by our sponsor. My question is: Does Digilent offer an FPGA development  board that is compatible with the TI AFE5812 ADC, or is there a board offered that has an ADC with the same specification as the AFE5812? The specifications we need for the ADC are as follows: greater than or equal to 4 channels, greater than or equal to 16 bits, greater than 1MSPS, and programmable gain stage that can increase dynamic range if the ADC bit rate does not meet 16 bits.

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Hi @Matthew Cabral,

Welcome to the forums. The XADC on all of our FPGA is a 2 channel 1MSPS ADC as shown here. The closest Pmod ADC we have is the Pmod AD5 which does not meet your project needs either. The Zedboard has two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs. I believe the zedboard should be compatible with the TI AFE5812. Here is the zedboard reference manual. Another potential solution would be to use a FMC ADC like the FMC104 FPGA Mezzanine Card which is a LPC FMC card. We have 2 FPGA's with a LPC FMC( Zedboard, Nexys Video).  The Genesys 2  has a HPC FMC. Here is a list of FMC ADC's. 

cheers,

Jon

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On 11/21/2018 at 10:38 AM, Matthew Cabral said:

AFE5812

There are a number of companies who make Analog Front End ICs. There aren't many of these devices for which an evaluation board exists. The AFE5812 happens to be one of the few that does. I suggest that you read the AFE5812EVM User's manual to get an idea of the complexity involved in using the device. Unfortunately, this, like most  converter EVMs require another expensive piece of hardware to use.

None of Digilent's FPGA boards will make a suitable development platform for using this particular IC. I've tried connecting a lot of converter boards to FPGA development boards that I already own and have had limited success in making it work without buying general purpose vendor made interface board/software platforms that are generally good at verifying performance and not research projects.  Trust me you have to do a lot of work just to see if it's possible to use vendors EVMs most of the time. Even when I'm successful there's usually a significant effort in conditioning the analog input to be suitable for sampling. This is what make AFEs so inviting. Making your own FMC mezzanine board is quite an undertaking. You might have better success with an FPGA using HSMC connector, though this would not be a trivial undertaking either.

What's I'd like to do is point you to a usable ADC EVM with either an FMC or HSMC connector and designed to connect to a known FPGA development board and meets your basic requirements; and then suggest designing your own analog conditioning front end including a PGA if needed. Unfortunately, I can't. I have gotten the AD7761 EVM to work with the Nexys Video via the FMC but while the device features some nice input filtering options the sample rates are at  best 1/4 of what you think that you need. I'll warn you that you need to read all ADC data sheets, particularly multi-channel, input filtered ones very very carefully to make sure that they meet your end requirements. There are a lot of landmines between you and success.

Perhaps the 1 M sample requirement can be relaxed a bit as there are more options for converter EVMs in the 100-500 KHz sample range. Most of these provide significantly less sample rates depending on your input filter options.

Based on ultrasound projects that I've done I imagine that a programmable gain over time would be important.

As far as differential PMODs go almost all of the Digilent boards sporting these are useless due to one one reason or another, particularly for converter interfaces.

 

Edited by zygot

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I wasn't going to mention this but reconsidered it.

Opal Kelly created some very usable single-ended and differential IO interface standards for their SYZYGY project. It started out as a Crowd Supply (Brain1) project but is now part of their own product line. Their standard port could interface to the AFE5812 EVM or the device if you take care of clock quality issues. Unfortunately, Opal Kelly hasn't demonstrated a commitment to supporting any of this. But you might look it up. I bought all of what they offer out of curiosity and haven't found the time to do anything useful with any of it yet... still hoping to make something out of it.... the whole SYZYGY project is still in an unfinished state and disappointing. But at least they got the IO right.

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Hi,

beware of eval boards. They are not modules, and vendors often actively resist supplying them in quantity.

One example from my own past for the same vendor, years ago, a gigasample DAC board with HSMC connector (similar to FMC) listed at $499. It took (I think) a month to get it, and when it arrived, the new revision had simplified supporting circuitry, with some features missing.

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5 hours ago, xc6lx45 said:

beware of eval boards

Beware is good advice all by itself. In general ADC and DAC evaluation boards are mean't to  allow a potential customer to test a devices performance for themselves, not provide a solution for any particular application. Some of these boards are more useful than others though and I have had some success. I'll have to start a thread listing those.. given the lack of decent converter options available for the Xilinx FPGA developer. ADC data sheets are notorious for obfuscating limitations and offering misleading performance feature claims... it takes some experience to know what to look for, or take note of what's not mentioned just for selecting a device. Designing a good ADC front end for most applications is not a task for the inexperienced. In this regard, if you can find a useful evaluation board that fits your needs this might be a good approach as no vendor wants their device to look bad due to supporting circuitry design mistakes. An ADC interface  shouldn't consume the time and effort of a senior project where the objective is to demonstrate knowledge and competency of a subject with the signal acquisition being only peripheral.

 

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@Matthew Cabral ,

So you seem to be unable to resolve your basic analog signal acquisition strategy. You basic concepts are correct. In theory, given an ADC with enough bits ( dynamic range ) you should be able to solve an issue with decaying signal level. In practice this is more complicated than you might understand. As the input signal to an ADC gets lower and lower you will start using fewer and fewer of those bits with consequences that might not be obvious. Typically in such systems the solution involves either analog AGC to keep the input signal near full input range or a time gain control or digitally controlled PGA to do so in a more coarse way. Of course it depends on the nature of the incoming signal. Often for ultrasound or sonar sensors I'd expect a drop over time of the signal of interest relative to background noise. You also need to know how many bits of conditioned input data your design objectives require to end up with satisfactory results. This is related but not necessarily dependent on dynamic range. Understand that all signal amplification schemes have their own frequency and noise issues to contribute to the end result.

As to sampling rate I'll offer this. Read though the data sheet for the Analog Devices AD7761 ( it isn't the device you want ). This will give you a feel for how digital input filtering works. The initial sampling rate and filtered sampling rates are rarely the same; most input filtering involves decimation. You need to understand what bandwidth your signal of interest is and how you plan on ridding it of unwanted interfering sources. You need to understand what the sample rate of conditioned signal is to meet your objectives.

Consult with your sponsor for assistance. By the way Analog Devices offers some pretty good technical materials in the area of signal processing and analog/digital conversion.

Edited by zygot

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The FMC connectors come in 2 basic flavours; Low Pin Count and High Pin Count. In general, mezzanine cards that work with LPC also work with HPC.  Notice the italics for empasis. Before connecting any board ( before buying any board ) you need to work through the schematics and trace every pin to make sure of compatibility for your FPGA platform. This includes signals, grounds and voltages. You also need to understand the IO banks limitations that the FPGA board imposes with its IO pin assignments. Obviously you need a schematic and understanding of the signal standard requirements of the mezzanine cards as well. You better have a large budget for something like the FMC164 or anything similar.

DO NOT RELY on the opinions of anyone ( including me ) regarding choosing an appropriate FMC mezzanine card. You HAVE to do the work for yourself.

Get a plan with your sponsors and professor that makes sense in terms of cost and effort.

Edited by zygot

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4 hours ago, Matthew Cabral said:

Genesys2 and ADS4449

@Matthew Cabral

I guess that you didn't read my post about EVM/FPGA development board experiences.

It just so happens that I did manage to cobble together a connection between the ADS4449 EVM and a KC705, so in theory you should be able to make it work with the Genesys2. I had to use a separate intermediary adapter between the EVM and the FMC connector. The EVM had support studs that I had to remove. The whole thing didn't end up being very mechanically sound. I had to supply additional supply voltages to the EVM.

To repeat warnings that I've posted before , you have to understand all of the documentation carefully before making a purchase. The ADS4449 EVM is set up for narrowband (125 MHz) operation for signals centered around 185 MHz. In theory you can change components to change this. The data interface is simple enough but you need to implement a serial interface to set up the ADC. I just used the on board USB interface so that I could use the Ti software to set up the chip. You'll want to put the ADC into test data modes to verify the FPGA interface design. This board is a good example of surprises waiting the unsuspecting or knowledgeable user. I managed to do what I needed but can't recommend it to anyone. It was a lot of tedious work.

Most high speed ADC evaluation board require a special baseboard which usually has an FGPA and accompanying software support. These things are usually geared to allow testing the performance of the device, not for use in a particular application.

There just isn't many options for 4-channel high speed ADC equipped FPGA boards in a reasonable price range.

One possibility for you might be:

Cyclone V GT Development board ( 2 HSMC connectors )

2 Terasic DDC boards ( each with 2 14-bit 150 MHz ADC and 2 14-bit 250 MHz DAC devices )

There are more ADC options in the Intel (Altera) world and Terasic makes a number of boards with multiple HSMC connectors. I have used the Cyclone V GT board with a DDC so I can confirm that they work together.

You don't need such sample rates and in theory you could use one ADC to sample 4 channels sequentially.. if you understand the ramifications.

On last warning. Asking what people think about possible compatibility of products is a good way to get into trouble. It's pretty easy to be well intentioned and provide bad advise or advise that's easy to misinterpret. Unless someone has actually had success with particular boards they can't offer useful guidance.

[edit] Since I mentioned the Cyclone V GT development board I should add a warning to anyone deciding to purchase one. Some idiot placed SMT devices very close to the HSMC mounting post holes. The first time I connected a board to one of these connectors I sheared off on the these SMT ICs (part of the board JTAG chain) and had to wire around it in order to configure the board.... not a way you want to discover board features. For the record it's a very good and useful Cyclone V board...

Edited by zygot

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