since Digilent posted a new version of the HDMI out demo using Vivado 2018.2, I gave this project a try again. Using the ReadMe I got quickly to a running program in the SDK, everything seemed to run as expected - however, no picture.
So I tried to debug the BD - which is a nice excercise in its own. First I checked the locked status of the AXI4Stream-to-video-out block: Locked is reset, but underflow is set. It seems, that there is no data transferred. When debugging the signals from the vdma, I realized after several tries, that PL clock FCLK1 is not enabled. Configuration of the Zynq block seems to be OK and checking the Xilinx forums also did not reveal anything useful. Of course without clock, no data will arrive at the display.
Does anybody know why this can happen? How to ensure that PS is initialized correctly? Does the program code from SDK ensure this in all cases? I guess I am missing a slight detail...
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juergenR
Hi,
since Digilent posted a new version of the HDMI out demo using Vivado 2018.2, I gave this project a try again. Using the ReadMe I got quickly to a running program in the SDK, everything seemed to run as expected - however, no picture.
So I tried to debug the BD - which is a nice excercise in its own. First I checked the locked status of the AXI4Stream-to-video-out block: Locked is reset, but underflow is set. It seems, that there is no data transferred. When debugging the signals from the vdma, I realized after several tries, that PL clock FCLK1 is not enabled. Configuration of the Zynq block seems to be OK and checking the Xilinx forums also did not reveal anything useful. Of course without clock, no data will arrive at the display.
Does anybody know why this can happen? How to ensure that PS is initialized correctly? Does the program code from SDK ensure this in all cases? I guess I am missing a slight detail...
Thanks for your help,
Jürgen
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