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Arty Z7-20 HDMI out demo: missing FCLK1


juergenR

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Hi,

since Digilent posted a new version of the HDMI out demo using Vivado 2018.2, I gave this project a try again. Using the ReadMe I got quickly to a running program in the SDK, everything seemed to run as expected - however, no picture.

So I tried to debug the BD - which is a nice excercise in its own. First I checked the locked status of the AXI4Stream-to-video-out block: Locked is reset, but underflow is set. It seems, that there is no data transferred. When debugging the signals from the vdma, I realized after several tries, that PL clock FCLK1 is not enabled. Configuration of the Zynq block seems to be OK and checking the Xilinx forums also did not reveal anything useful. Of course without clock, no data will arrive at the display.

Does anybody know why this can happen? How to ensure that PS is initialized correctly? Does the program code from SDK ensure this in all cases? I guess I am missing a slight detail...

Thanks for your help,

Jürgen

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Hi @juergenR,

To confirm you are using the Vivado 2018.2 release for the Arty-Z7-20 HDMI out here with the Digilent board files installed. Here is a tutorial for the Board files. The board files have the correct configuration for the ZYNQ processor. I was able to get the Arty-Z7-20 HDMI out project working using the initial bitstream or generating a current bitstream.  

thank you,

Jon

Arty_z7_20_hdmi_out_2018.2.jpg

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Yes, I can confirm that I am using the 2018.2 release of the example together with Vivado 2018.2 and the board files installed. Bitstream generation works fine, PL gets programmed.

I have no doubt that your example is correct and will work. Actually I assume the problem is linked to some sort of "misconfiguration" of the PS I am not aware of - but I have no real clue where to look at.

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Hi, Jon,

thanks for your reply. Finally I figured out what my mistake was.

The board boots a Linux project and on other experiments I never encountered problems just starting the SDK generated program. For this case I also assumed that ps7_init will put everything right, but which apparently is not true.

The whole demo works fine, as soon as I stop booting within U-Boot. This allows me on one hand to program the device using the Vivado hardware manager as well as starting the test program from the SDK.

Another possibility would be to change the run configuration to include a full PS reset and the programming of the PL, but I did not test this.

BR, Jürgen

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