ARTY A7-100T/ Vivado 18.2 Implementation Errors

[RobinDB]

Good Morning,

I am creating microblaze based project: with 256M Memory, UARTlite, 4 Leds & PModGPIO for JA & JB

Run Implementation:  
Errors 

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (20) is greater than number of available sites (0).
The following are banks with available pins: 
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   RangeId: 1  has only 0 sites available on device, but needs 20 sites.
    Term: led_4bits_tri_i[0]
    Term:  led_4bits_tri_i[1]
    Term:  led_4bits_tri_i[2]
    Term:  led_4bits_tri_i[3]
    Term:  ja_pin10_i
    Term:  ja_pin1_i
    Term:  ja_pin2_i
    Term:  ja_pin3_i
    Term:  ja_pin4_i
    Term:  ja_pin7_i
    Term:  ja_pin8_i
    Term:  ja_pin9_i
    Term:  jb_pin10_i
    Term:  jb_pin1_i
    Term:  jb_pin2_i
    Term:  jb_pin3_i
    Term:  jb_pin4_i
    Term:  jb_pin7_i
    Term:  jb_pin8_i
    Term:  and jb_pin9_i

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Board files in   ....\arty-a7-100\E.0\ are dated August 30th 2018

Note:
 MPS posts a similar query November 21st 2015 for the ARTY board

Solution: Digilent updated the  board files.

 

Thank you.

Robin

[jpeyron]

Hi @RobinDB,

I was able to generate a bitstream using vivado 2018.2 for the Arty-A7-100 here.  I used the Arty-A7-100 board files as described here. I attached some helpful screen shots below.

cheers,

Jon

[edge30]

I'm seeing the same issue with Vivado 2018.3 and even using the latest board files (from april 18th 2019).

Has anybody from Digilent actually tried to resolve? any clues so we can may resolved it by ourselves?