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mrpackethead

Arty Web Server Demo with 2018.2?

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Hi @mrpackethead,

I was able to get the echo server working on the Arty-A7-35T using "Vivado 2018.2". I used the getting started with microblaze servers tutorial.  Here is the completed project. I had to replace the xadapter.c file with the attached file as discussed on this forum thread. I also used an altered echo.c file  which i attached below as well.

cheers,

Jon

 

echo.c.txt

xadapter.c

Arty_ethernet_echo_server_vivado_2018.2_1.jpg

Arty_ethernet_echo_server_vivado_2018.2_2.jpg

Arty_ethernet_echo_server_vivado_2018.2_3.jpg

Arty_ethernet_echo_server_vivado_2018.2_4.jpg

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I was able to get that going as well, and yes, needed to replace that file.       I went on and made some mods to it,  to control the LEDS etc.        I'm not so interested in teh web server, but in FreeRTOS.  

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It seems that there are some bugs in 2018.2, if you try to combine RTOS and the LWip together. Missing files..  Have you tryed a 2018.2 project, such as the echo server with FreeRTOS?  ( even with lwip )

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I am getting a strange issue with this demo on my Arty-S7-25T board. Attached is the DDR3 block that causes a bug when I try to do the demo. I notice a few things about this image here:

 

1. There is a new pin for device temperature

2. There is a new pin for something called "ui_addn_clk_0" that I wont guess on

3. The word "beta" appears in the block

 

Is this the correct DDR3 block for this demo? Before I get the demo to fail again I would like to know if this might be the issue right out of the gate.

 

Thanks.

FPGA_uCore_issue.jpg

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Hi @tadius,

I get the same MIG when adding the DDR3 from the board tab in "Vivado 2018.2". I was able to generate a bitstream with ignoring the warnings from not connecting anything to those 2 pins. I will reach out to our content team to verify that we are using the correct MIG IP Core.

cheers,

Jon  

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