How to understand -edge option if first edge of generated clock is falling edge?

[tip.can19]

I am trying to understand the waveform created by create_generated_clock with -edge option.

Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png

I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z]

Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png

Thanks

[tip.can19]

i think i misunderstand the diagram with edges. I suppose the 11th edge is nothing but first edge, so from 10 to 11th edge is equal to high period (1 step/1ns) and then 1 to 2nd edge (1ns) as another step which makes positve 2ns, so the fall is at edge 2 and not 3. I hope this understanding is correct.

[JColvin]

Hi @tip.can19,

I'm not certain what you mean by "the 11th edge", but this is my understanding of the situation, based on Chapter 3 of UG903. The first value generated is always a positive clock edge, so when you created the generated clock, it considered the starting point (first value) of the master clock, in this case the primary clock that you defined. By setting the -edges option, you told it to use the 5th, 7th, and 10th edge of the master clock as the places to change.

What I'm not certain on is why your generated clock starts out on a logic high value, and then has to go on a falling edge to achieve that first rising edge on the 5th edge rather than holding the value low until the 5th clock edge on the master clock occurs. I don't know if this is because Vivado wants to repeat this exact pattern starting with a rising edge on the generated clock occurring on that 5th edge of the master clock for every 10 ns section, but I do not know this for certain or if there another argument that can be used to help prevent this (if this is the case). Other community members on the Forum or the engineers on the Xilinx forum may be better able to shed some light on this.

Thanks,
JColvin

[tip.can19]

Hi JColvin,

Thanks for your inputs and reply. Really appreciate it.

As you correctly pointed out, as per the -edge {rise,fall,rise and so on..}, what we think is edge {5,7,11} is period of generated clock with 2ns of positive and 3ns of negative period (5ns total with first rise outside the master clock period) and hence from 10th edge the waveform should repeat itself to maintain the clock. Thus from 10th edge to next edge i.e. 11th edge (or 1st edge since clock is repeated) the engine will automatically infer positve period and auto infer falling edge at 2 (not ns but edge). I could confirm this from Xilinx as well.

Thanks a lot,

Regards

Tip