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Weevil

SPI-Flash CmodA7-35T Vivado 2017.3

Question

Hi all, 

i tryed to do the "How To Store Your SDK Project in SPI Flash" tutorial but i do not get it to work. Everything seems to be successful, but after rebooting the CmodA7 the .elf program i created does not start. During creating the project i followed the instruction from the attached post.

(https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start)

 

Additional i tryed to merge the .bit and .elf file with Vivado like the tutorial (https://techmuse.in/creating-and-configuring-xilinx-fpga-with-mcs/). Programming the fpga manual works, but if i try to write it in the flash the .elf program does not start. After programing the flash the bitstream is out of date (i don't know why). Maybe someone have an idea what i can do to get the merged bit file or mcs file on the spi-flash? 

Attached is my vivado project folder (http://www.mediafire.com/file/bq3ebw7b2dfpf72/Test_Microblaze.zip/file)

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Hi @Weevil,

My understanding is that you want to use a .bin file and not a mcs file.  Here is a completed and verified Vivado 2017.3 compressed bitstream Cmod-A7-35T QSPI hello world project. The block design includes most of what your project had except the interrupts.  I added a second output clock from the clock wizard at 50 MHz and attached it to the ext_spi_clk on the QSPI flash IP core. Are you using the Digilent board files? Here are the How To Store Your SDK Project in SPI Flash and the Installing Vivado and Digilent Board Files tutorials.

cheers,

Jon

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Hi Jon @jpeyron,

thank you so much for your example! 

Your example works for me, but actual i did not get why my design does not work. I am using the board files and follow before your "How To Store Your SDK Project in SPI Flash". Actual i expect some failure in my microblaze design. Thanks again!

Edited by Weevil

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Hi @Weevil,

When opening your project i got a warning about using a custom FPGA board. I would make sure that the board files are install correctly. Are you able to see the Cmod A7 35T in the board tab when setting up a project. I also did not see interrupt connections to the Concat IP Core from the UART IP Core and any other IP Core you were hoping to use through interrupts. Also using interrupts will make the SDK coding part of your project much more complex. If you do not need interrupts i would suggest to not use interrupts.

cheers,

Jon 

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@jpeyron

I copied the board files in the folder "C:\Xilinx\Vivado\2017.3\data\boards\board_files" and started the project with the CmodA7 board. (working with windows 10)

2.thumb.PNG.66e23829f2ec3db507c01ac232d8e3b9.PNG

The interrupts i maybe would need in a further step, but for now i deleted them.

I figured out, when i follow the whole instruction of the tutorial i get to the point to program the FPGA with the choosen .elf file. On this step i get the following error message. If i start it with the standard bootloop file it works an creates the download.bit file. But this file does not include the .elf datas and after i generated this download.bit file i can not replace it with my bit-file+spi_loader.elf... 

image.png.1f65f82c63fe2d0817c20fb12fd82eef.png

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Hi @Weevil,

Can you please attach a screen shot of your vivado block design as well as your SDK set up.  Could you also attach a screen shot of step 3.1 of your project. Are you compressing the bitstream?

cheers,

Jon

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Hi Jon @jpeyron,

I direct used your design and deleted the sdk folder only and expoerted the hardware with bitstream. Please find attached screenshots.

4.thumb.PNG.524a65db4511021d31c8af93f4b3de57.PNG

5.thumb.PNG.0e1d324a42a42f39c88c617dd53aafcc.PNG

Maybe this error would be interesting: ERROR: [Updatemem 57-153] Failed to update the BRAM INIT strings for C:\Projekte\MSX\FPGA\testo\cmoda7_qspi.sdk\boot_spi\Debug\boot_spi.elf and C:/Projekte/MSX/FPGA/testo/cmoda7_qspi.sdk/design_1_wrapper_hw_platform_0/design_1_wrapper.mmi. 

 

Edited by Weevil

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Hi Jon @jpeyron,

got it, i had changed the linker script of the boot-loader to the axi_emc.... Before i didn't catch this because my old download.bit from the previous standard bootloop was there and i didn't recognise the error... 

Sorry for wasting your time and thank you very much for your patience!

Greetings!

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