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Thausikan

Ethernetlite design (LWIP): Whether AXI UART IP is mandatory ?

Question

I am using KC705 board, and working with vivado 2015.4.

In current design, i have implemented the below process using the AXI UARTLITE.

1. Counter data (Binary Counter IP) from Kintex DAQ board (Part Number : XC7k160tffg676-2) is passing to the KINTEX KC705 board through optical cable. No issue. I am able to read the data in KINTEX KC705 through AXI FIFO

2. KC705 board will pass the data From FIFO to PC through LWIP Echo server, where i can able to read the data in Hercules.

Same Process should be done without using AXI UARTLITE module. So, I have removed AXI - UARTLITE IP in my design, and generated the bit stream. After lunching the hardware and export the hardware, i am unable to create application template (LWIP echo server). Its showing an error messgae " This application requires a Uart IP in the hardware". Please anyone suggest me. How I can use LWIP without using AXI Uartlite. Can anyone suggest me please.

LWIP_UART.thumb.JPG.488b4c64ff31f0363c412fadad1d30f9.JPGKC_Error_design.thumb.JPG.92c62f7e69743146d27e7173c7c91f09.JPG

 

 

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Hi @Thausikan,

The UARTLITE IP Core is part of the LWiP echo_server template . I believe that you would need to remove all uses and #includes of the uartlite in the echo_server template to be able to use it without the UARTLITE IP Core. The LWIP  uses the UARTLITE IP Core to help set up the ethernet connection as shown in step 14.3 Genesys 2 - Getting Started with Microblaze Servers tutorial here. The UARTLITE IP Core  is not used in the LWiP echo_server template for data transfer. Data goes through the ethernet.  It appears you asked xilinx the creators of the LWiP about this as well here. If you are able to use Vivado 2018.2 there are additional LWiP Core templates that might be useful as well.

thank you,

Jon

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First, Thanks for your kind response.

>>It appears you asked xilinx the creators of the LWiP. Yes, still they have not responded.

Ok, I understood your point. But one more doubt, if i need to remove all uses and #includes of the uartlite in the echo_server template then i need to access the "LWIP Echo server Template". But i am not able to choose the "LWIP Echo server Template" from XSDK Please look the above message. Its showing an error messgae " This application requires a Uart IP in the hardware".

Then how please suggest me.

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Hi @Thausikan,

I was able to create an ethernet  project with the uart and export it to SDK. Then create an application with the LWiP echo server. Then i went back to vivado and edited the bock design removing the uart. I then deleted and re-generated the wrapper. I then generated a bitstream and re-exported the hardware including the bitstream. I then launched SDK an it should still have the echo_server application with a hardware platform without the uart ip that you should be able alter the uart information.  

thank you,

Jon

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Hi,

   I have followed your steps. But again one doubt.

 Same thing I have followed :created an ethernet  project with the axi-uart and export it to SDK. Then created an application with the LWiP echo server. Then i went back to vivado and edited the bock design removing the uart. I then deleted and re-generated the wrapper. I then generated a bitstream and re-exported the hardware including the bitstream.

  With axi-uart , i have generated hardware platform_0

 Without axi-uart , i have generated hardware platform_1

I need to run this design only without axi-uart. So my doubt is which hardware platform i need to select while programming the FPGA.

Without axi-uart design, i am able to get data only if i select hardware platform_0. hardware platform_1 is not giving any output. Then what difference is in design. 

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