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malkauns

Zybo Z7-20 PCAM Demo Unimplementable on Vivado 2017.4

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I am using Vivado 2017.4 on Linux and am trying to build the pcam demo project.  The readme states "Created for Vivado 2017.4".  After downloading and extracting Zybo-Z7-20-pcam-5c-master.zip and vivado-library-master.zip I am executing the following steps:

cp -r vivado-library-master/ip/* Zybo-Z7-20-pcam-5c-master/repo/vivado-library/
<start vivado 2017.4 in tcl mode and cd to Zybo-Z7-20-pcam-5c-master/proj/>
source create_project.tcl

 

create_project.tcl produces the following output with error:

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
system_auto_pc_0
system_auto_pc_1
system_xbar_0
system_video_dynclk_1
system_MIPI_D_PHY_RX_0_0
system_clk_wiz_0_0
system_axi_mem_intercon_0
system_AXI_BayerToRGB_1_0
system_rgb2dvi_0_0
system_axi_mem_intercon_1_0
system_ps7_0_axi_periph_0
system_AXI_GammaCorrection_0_0
system_axi_vdma_0_0
system_auto_pc_2
system_MIPI_CSI_2_RX_0_0
system_v_axi4s_vid_out_0_0
system_processing_system7_0_0
system_rst_clk_wiz_0_50M_0
system_vtg_0
system_rst_vid_clk_dyn_0
system_xlconcat_0_0

ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

    while executing
"make_wrapper -files [get_files $design_name.bd] -top -force"
    invoked from within
"if {[llength $bd_list] != 0} {
  add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
  open_bd_design [glob -nocompla..."
    (file "create_project.tcl" line 123)
Vivado% 

 

Full output: https://pastebin.com/s1N875XD

 

When I try to implement I get the following error:

[Place 30-569] BUFIO instance 'SerialClkBuffer' is driving 'I' pin of instance 'SerialClk_OBUF_inst'{OBUF}. This will lead to unroutable situation. A BUFIO can drive only clock pins of IO tile

 

Can someone please point me in the right direction?

 

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Hello,

Could you try the following steps, in order, for building your Pcam 5C Vivado project?

1. The master vivado-library branch is missing the D-PHY and CSI-2 IPs needed for the Pcam 5C demo project. Please download the d-phy vivado-library branch instead: https://github.com/Digilent/vivado-library/tree/feature/d-phy

2. Once you downloaded this version of the library please unzip it and copy its contents (the "if" folder, the "ip" folder, the ".gitignore" file, the "License.txt" file and the "README.md" file) directly at the following location in your unzipped Pcam 5C Vivado project (without any additional subfolder in the path): <path to your unzipped Pcam 5C proj>\Zybo-Z7-20-pcam-5c-master\repo\vivado-library\ .

3. Clean up the project and rerun the \Zybo-Z7-20-pcam-5c-master\proj\create_project.tcl script from Vivado.

4. You may see an error in Vivado about the D-PHY and CSI-2 IPs being locked. To fix it, please run from Vivado: Tools -> Report -> Report IP Status. This will open a window saying the D-PHY and CSI-2 IPs need to be upgraded. Select "Upgrade Selected". Once this is finished, you should be able to correctly synthesize and implement the Pcam 5C Demo project.

Please let me know if you encounter any other issue with the Demo Project.

Best Regards,

Ioan.

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After following the above steps, you may still see an error during Implementation which is similar to the one you initially described. This occurs because the system-level block diagram of the demo project is no longer the project top-level.

To fix this error, in Vivado please right-click on the system_i block-diagram item and select "Create HDL Wrapper...". Then right-click on the HDL wrapper you just created and select "Set as Top". You will then see this HDL wrapper becoming the project top-level.

If you then rerun synthesis and implementation, they should work fine.

We will update the IP versions in the demo project on GitHub.

Best Regards,

Ioan.

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Ionut, thanks for your help.  I was able to generate the bitstream.   To note, I did have to "Reset Output Products" in order to get past a permissions error which according to the Xilinx forums occurs when the project is created on Vivado in Windows then implemented on Vivado on Linux.  It may be worth trying to address this issue if possible.  My next problem is that I encounter the following error when I try to program the device (Zybo Z7):

 

ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device.
ERROR: [Labtools 27-3165] End of startup status: LOW
ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.

 

In the project settings I have made sure that "Zybo Z7-20 (xc7z020clg400-1)" is the current selected "Project device".

 

Full output:  https://pastebin.com/sXnLfNcH

 

Please help and thanks for your help so far!

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Hi @malkauns,

Could you attach a picture of your setup? Based on the output, it looks like (based on lines 22 to 29) that Vivado believes you have a Zybo Z7-10 attached rather than a Zybo Z7-20. A good way to tell would be if there is a heatsink or not on your device; the Zybo Z7-20 has a heatsink, and the Zybo Z7-10 does not. The -10 variant also does not have one of the Pmod ports loaded.

Thanks,
JColvin

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I've tried implementing it for the Z7-10 but get the following error:

[Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 4400 slices in the pblock, of which 2903 slices are available, however, the unplaced instances require 3493 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.

Number of control sets and instances constrained to the design
	Control sets: 808
	Luts: 16409 (combined) 18202 (total), available capacity: 17600 
	Flip flops: 18901, available capacity: 35200
	NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice

 

Critical warnings and error output: https://pastebin.com/m4dBhiUA

Edited by malkauns

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Hello,

The Pcam 5C demo project does not fit onto the Z7-10 PL: you need a total of 18202 LUTs, and you only have 17600 on the Z7-10. In other words, at some point in the placement phase, you have 2903 available slices, while there still are 3493 slices required in order to finish placing the design.

I don't know of any IP block you can remove/reduce in size in the demo project, in order to make it fit the Z7-10, while still keeping the project functional.

I recommend switching to a Zybo Z7-20, where the project would fit.

Best Regards,

Ionut.

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Thank you for the feedback regarding the issue when a project is created on Vivado in Windows then implemented on Vivado on Linux!

We will look into fixing it in the demo project.

Best Regards,

Ionut.

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Hello,

I would like to make a correction to my previous statement that I didn't know of a way to reduce the size of the Pcam 5C Demo Project to fit on the Zybo Z7-10 board. Actually, there is a way to reduce the size of the design, by disabling Debug Module for the CSI-2 IP. You can perform the following steps in order to do this:

1. Download the latest version of the Pcam 5C Demo project from https://github.com/Digilent/Zybo-Z7-20-pcam-5c, in zip format.

2. Use the vivado library zip file (which includes the D-PHY and CSI-2 IPs) you previously downloaded from https://github.com/Digilent/vivado-library/tree/feature/d-phy, or download it again.

3. Unzip the two zip files, put the vivado library in its folder under the repo folder.

4. Run the create_project.tcl script from Vivado 2017.4.

5. In the project block diagram, double-click on the MIPI_CSI_2_RX_0 IP and deselect Debug Module. Press OK. Save the project.

6. In the project settings, change the project device to xc7z010clg400-1, in order to match the Zybo Z7-10 board.

7. Report IP Status -> Upgrade Selected.

Synthesis, implementation and bitstream generation should then work fine. You should then be able to run the Pcam 5C Demo project on the Zybo Z7-10 board.

I hope this is helpful for you. I am sorry for the initial answer on the project size.

Best Regards,

Ionut.

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Thanks for your reply.  I'm able to generate the bitstream for the Z7-10 after following your instructions.  However, isn't the debug module required to communicate with the logic running on the board so that I can set camera options (resolution etc.)?  After powering on the Zybo I am attaching to it over the serial port using screen /dev/ttyUSB1 115200 (on Linux).  When I program the board from Vivado I am expecting the camera options text to show up in the terminal so I can make selections.  In my case nothing shows up on the terminal.  Please tell me if I am making the wrong assumptions about how this is supposed to work.  My ultimate goal is to be able to send the sensor registers from Linux running on the PS to the camera sensor.

 

error output:

open_bd_design {/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/src/bd/system/system.bd}
set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
set_property PROGRAM.FILE {/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/proj/pcam-5c.runs/impl_1/system_wrapper.bit} [get_hw_devices xc7z010_1]
program_hw_devices [get_hw_devices xc7z010_1]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).

 

Edited by malkauns

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Hello,

 

The debug module for the CSI-2 IP is only used for HW debugging inside the IP itself, it is not used for setting up parameters like camera resolution. For these parameters, the AXI-Lite interface is used instead. So the messages in the UART terminal should appear regardless of the IP Debug settings.

After the bitstream is generated by Vivado, please make sure you do the following:

1. Export the hardware (File -> Export -> Export Hardware -> Include bitstream) to the \Zybo-Z7-20-pcam-5c-master\hw_handoff folder, overwriting the existing file.

2. Launch SDK from Vivado (File -> Launch SDK), setting up the Exported location to \Zybo-Z7-20-pcam-5c-master\hw_handoff and the Workspace to \Zybo-Z7-20-pcam-5c-master\sdk.

3. Left click on the pcam_vdma_hdmi project and then from the top menu select Project -> Build Automatically.

4. Re-generate BSP sources for fsbl_bsp and for pcam_vdma_hdmi_bsp, by right clicking on each of these projects and selecting Re-generate BSP Sources.

5. Left click on the pcam_vdma_hdmi project. From the top icons, select Program FPGA. Then, from the top menu, select Run -> Run -> Launch on Hardware (System Debugger).

The Pcam 5C demo project should then work fine.

Please let me know if you encounter any issues with this.

Best Regards,

Ionut.

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Ionut, thanks for helping me understand things better.  After succesful implementation I followed your stage 1 and 2 instructions exactly but when I get to stage 3 I do not see "pcam_vdma_hdmi" anywhere when the SDK comes up.  This is what the SDK window looks like:

 

1108973659_DeepinScreenshot_XilinxSDK_20181119103610.thumb.png.df950328b12d042cce7f2be3ebb5c140.png

 

Please advise.

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Hello,

You only have the hardware platform in SDK. You need to import the other projects from the SDK folder (fsbl, fsbl_bsp, pcam_vdma_hdmi and pcam_vdma_hdmi_bsp) into SDK, by selecting File -> Import -> General -> Existing Projects into Workspace -> Next -> Select Root Directory as \Zybo-Z7-20-pcam-5c-master\sdk -> Select the above-mentioned projects -> Finish.

Then follow steps 3 through 5 from the above post.

Best Regards,

Ionut.

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Thanks for all the help!  With your instructions I was able to get the demo working on the Z7-10 board.  Hopefully this thread will help others who run into similar issues.

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Hi,
I am trying the same setup: Zybo Z7-10 and downloaded almost the same code that @malkauns did https://github.com/Digilent/Zybo-Z7-20-pcam-5c/tree/482b7c3ebb66bc3c04706f9e5ccda8edd933bc04 dated Oct 26, 2018.
Did also the same steps described here:

 

After upgrading the IPs I get these messages Critical warnings:
[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073 . PS DDR interfaces might fail when entering negative DQS skew values. 
[PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.034 . PS DDR interfaces might fail when entering negative DQS skew values. 
[PSU-3]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.03 . PS DDR interfaces might fail when entering negative DQS skew values. 
[PSU-4]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.082 . PS DDR interfaces might fail when entering negative DQS skew values. 
[Designutils 20-1280] Could not find module 'ila_sfen_rxclk'. The XDC file c:/Users/admin/repo/Zybo-Z7-20-pcam-5c-26oct/src/bd/system/ip/system_MIPI_D_PHY_RX_0_0/hdl/ila_sfen_rxclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
 

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

[Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 
 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export.
 2. There are no block design hardware handoff files. Check the vivado log messages for more details. 


Do you have some advice to counteract these issues?
regards,

Fino

problem.png

problem-logs.png

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Posted (edited)

Hi @flying,

You can ignore the DDR critical warnings and probably you can also ignore the ILA warning. The DDR warnings are due to our preset file. The ILA warning should not affect the functionality of your design. Presuming those 3 errors that I'm seeing in your image are not related to your last run, you can try to export your  hardware and regenerate your bsp files in SDK.

Best Regards,

Bogdan Vanca    

Edited by BogdanVanca

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Posted (edited)

Hi Bogdan Vanca,

Thanks for the quick answer.

Exporting is blocked with the exception:
[Vivado 12-4452] The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 
 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export.
 2. There are no block design hardware handoff files. Check the vivado log messages for more details
 

It sems I still have some errors that are stoppers as the model is not successfully synthesized.
After Reporting and upgrading again the IPs and there are still problems with MIPI_CSI_2_RX_0_0 and DVIClocking.

[Synth 8-439] module 'system_MIPI_CSI_2_RX_0_0' not found
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
[Synth 8-2396] near character '0' ; 3 visible types match here ["C:/Users/admin/repo/Zybo-Z7-20-pcam-5c-26oct/src/hdl/DVIClocking.vhd":69]
SyncLockedOut: entity work.RestBridge <--------Error: cannot find <restbridge> in library <xil_defaultlib>. Please ensure that the library was compiled and that a library and a use clause are present in the VHDL file.
   generic map (
      kPolarity => '0')

Firstly the report IP did not find the DviClocking and DviClocking.vhd was empty.
And MIPI_CSI_2_RX was downloaded from here https://github.com/Digilent/vivado-library/tree/feature/d-phy and extracted under %project/repo\vivado-library

Best regards,F

synthesis.png

dviclocking.png

folder with IPs.png

cannot export hw.png

Edited by flying

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Hello @flying,

Can you please give me the entire project? In this way it will be easier for me to trouble-shoot your problem. The issue may come from different directions.

Best Regards,

Bogdan Vanca 

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Hi Bogdan Vanca ,

You can find the code here:

https://github.com/flyinggiorno/Zybo-Z7-20-pcam-5c-26oct

Best regards, F

 

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Posted (edited)

Hi,

FinallyI succeeded exporting the HW to SDK by repeating the steps with Zybo Pcam repo and the dependency towards vivado library and took an appropriate commit (as posted in this comment

 

But now to Program the FPGA , 
I have difficulties in executing the following sequence mentioned above:
5. Left click on the pcam_vdma_hdmi project. From the top icons, select Program FPGA. Then, from the top menu, select Run -> Run -> Launch on Hardware (System Debugger).

Please see the screenshot attached - I do not have Run -> Run ...
And another question: how should be the configuration of JP5 ? QSPI or JTAG ?
When in JTAG I have only a red led LD13 PGOOD, and when configuration is QSPI I have PGOOD LD13 on, DONE LD12 on LD6 changing color, and also LD0,LD1,LD2,LD3  flickering and LD4 pulsing.

 

Subsequently my interest would be to read the stream captured on the PL into the PS  and apply some video processing onto it and output the processed video stream via HDMI. Could you point me to some data processing using Open CV - is there a guideline of how to achieve this frame streaming from PL into PS and installing OpenCV into PS?

Thanks in advance,

Best regards

problem program FPGA.png

Edited by flying

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Posted (edited)

Hi @flying,

I’ve opened your Vivado project and I faced the same issues. Your problems are probably related to the fact that you generated your IP’s output products before you changed the target device. In order to successfully generate the bitstream file, you need to select the Zc010 device and after that, you must update your IPs, generate their output products and finally generate the bitstream. The next step is to export your design into the handoff folder and regenerate the bsp file in SDK. Also, before you generate the bit file you must deactivate the DEBUG module from MIPI_CSI_2_RX_0 ip. If you dont do that, the project will not fit in the z10 variant. Underneath you can see all the steps that I went through.

1.       First, I cloned the ZYBO Z7 DEMO project from here: https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.150711477.200137549.1554706874-1290099257.1518602399

2.       After that, I updated the Vivado library repository folder using the following repository: https://github.com/Digilent/vivado-library 

3.       After this, I moved back with 3 commits in the master branch. In this way I could generate the project using our old tcl Vivado flow. The same tcl file that you used.

4.        I deactivated the Debug Module within MIPI_CSI_2 IP and I run create bitstream.

5.       I exported the bitstream file in the handoff folder and I regenerated the bsp file in SDK.

You can find the complet functional project on this link:

https://www.dropbox.com/s/e2t6etbeuethh30/Zybo-Z7-20-pcam-5c.rar?dl=0

 

For video processing you can use Vivado HLS. You cannot install OpenCV in PS. An alternative is to write down your own video processing algorithm in HLS and from there you can export it as an ip in Vivado. From what I know HLS includes the OpenCV interfaces.  

 

Best Regards,

Bogdan Vanca 

Edited by BogdanVanca

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Hi Bogdan Vanca ,

Thanks a lot for your answer. Indeed , the archived project was successfully built.

I still have one question:

The HDMI sink - my screen does not synchronize unless I select the resolution: VGA
pipeline_mode_change(vdma_driver, cam, vid, Resolution::R640_480_60_NN,OV5640_cfg::mode_t::MODE_720P_1280_720_60fps);

I tried on another one and the resolution 720p

pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1280_720_60_PP,OV5640_cfg::mode_t::MODE_720P_1280_720_60fps);

However the 1080p does not work:
pipeline_mode_change(vdma_driver, cam, vid, Resolution::R1920_1080_60_PP, OV5640_cfg::mode_t::MODE_1080P_1920_1080_30fps); --- problematic.

 

Is this related to the timing issues of the design?
The screen was successfully set as a computer monitor on 1080p .

How can I get  rid of these timing issues?
route_design Complete, Failed Timing!
WNS -2.421; TNS -4.796

WHS -1.07; THS -2.098

 

Thanks and best regards !

timing problem.png

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