I am prototyping a concept on the Nexys Video Board.
I would like to use the FMC connector and build my own FMC-like board.
I will be using both GTP and SERDES outputs. considering the speeds (2.4Gbps, 300Mbps) I need to make sure signal integrity is up to standards all the way from FPGA Ball to the chip on my FMC board including connectors and co.
Therefore I need info on the Nexys Video Layout.
could you provide:
-full layout so I can do post-layout model extraction for the GTP and SERDES io lines, for simulation with Hyperlynx?
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toby
Hello,
I am prototyping a concept on the Nexys Video Board.
I would like to use the FMC connector and build my own FMC-like board.
I will be using both GTP and SERDES outputs. considering the speeds (2.4Gbps, 300Mbps) I need to make sure signal integrity is up to standards all the way from FPGA Ball to the chip on my FMC board including connectors and co.
Therefore I need info on the Nexys Video Layout.
could you provide:
-full layout so I can do post-layout model extraction for the GTP and SERDES io lines, for simulation with Hyperlynx?
or
-hyperlynx models of the lines?
best regards.
toby
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