Discrete Fourier Transform V4.0

[MVS]

Hello there,

im working on a image encryption system and I want to implement the DFT ip core module from Xilinx.  Here the results of the implementation.... I dont realize why the output data is XX if im entering the correct 2´s complement imput data...

If someone has implemented this module before, I would appreciate some advice.

control.vhd

[jpeyron]

Hi @MVS,

I have no experience with the DFT IP Core. I did find some documentation that  might help here and here.

thank you,

Jon

[MVS]

Hello jpeyron, 

I made my design based on whats exposed in the first link.  Compare this two images. 

I dont understand why, even if I enter  zeroed vectors, i dont have a valid output; being the Fourier transform a sum, if the imput values are zeros, the outcomes should be zeros too...

Thanks for your attention. 

[D@n]

Are you starting the core with a reset?  It's not in your trace, so I figured I'd ask.

Dan

[MVS]

Yes I am, Sr. Dan.  The reset signal is SCLR  (Synchronous Clear).

This page is from IP core product guide.

I leave here my .vhd and the testbench file.

 

(Y)

control.vhd

TB.vhd

[D@n]

Ok, I see that now.  I was expecting something with a name closer to "reset", but hadn't checked the interface document.

Not sure what to tell you.  Neither Digilent (to my knowledge) nor I has the source for Xilinx's FFT generator necessary to figure out the answer to your question.  Alternatively, you are welcome to use my own FFT core generator if you think it would help--you'd at least see the "inside" of the core if you did so.  It's not nearly as featured as Xilinx's cores are, but it's at least open source.

Dan

[MVS]

A lot of thanks Dan. Im going to take a look at your module.