darth458 Posted October 13, 2018 Share Posted October 13, 2018 Hi, This is a bit exotic. Has anyone hacked the hardware in order to lock the 100 MHz clocks of two or more AD2? Seems like maybe the simplest thing might be to feed the PLL because the frequency going in is lower so the signal handling to get it in there would be easier. However you may get a fixed phase offset at 100 MHz that is unpredictable. Has anyone tried this? thanks Link to comment Share on other sites More sharing options...
xc6lx45 Posted October 13, 2018 Share Posted October 13, 2018 I can only tell you this much that sync'ing multiple instruments is by no means a trivial problem, at least as long as external triggering is concerned. Which means, in other words, starting both boxes at predictably the same time. The problem is a race condition between the (asynchronous) trigger signal and each unit's interpretation of the reference clock. There is always a possible trigger time instant, where a very small delta moves it over the edge on one side but not the other. So you have a timing ambiguity of 1 sample in the mathematically ideal case. With real-world instruments it is often more because of implementation limitations (generally, not speaking about AD2) and I either let one of the instruments generate the trigger (which is then synchronous) or import it into the reference-synchronous "trigger" clock domain of the instrument (which is often 10 MHz aka "trigger resolution of 100 ns") and re-export it from there. Link to comment Share on other sites More sharing options...
JColvin Posted October 15, 2018 Share Posted October 15, 2018 Hi @darth458, There a number of threads discussing using multiple AD2's available below (each containing some links to more threads): As you'll find, the limitations are what @xc6lx45 noted. Let me know if you have any questions. Thanks, JColvin Link to comment Share on other sites More sharing options...
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darth458
Hi,
This is a bit exotic. Has anyone hacked the hardware in order to lock the 100 MHz clocks of two or more AD2? Seems like maybe the simplest
thing might be to feed the PLL because the frequency going in is lower so the signal handling to get it in there would be easier. However you
may get a fixed phase offset at 100 MHz that is unpredictable. Has anyone tried this?
thanks
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