FIFO external input microblaze output

[raultricking]

Hi guys, 

Im using microblaze for ethernet purposes: UDP real time communication with my PC ( send audio from 4 microphones directly to PC  ~5Mbps). My goal is to have a real-time (or almost) communication with my pc trough UDP ( Pyhton UDP Client in PC ).I already implemented the UDP server in the FPGA using LWIP stack and an I2S Controller for the microphones, but now im stuck at joining both parts of the project:

 

-i receive a sample from the microphones every 25 us , and i prepare an UDP packet of a certain number of samples to send, but calling my function udp_transfer() to transfer the data on microblaze delays more than 25 us, so i lose samples on this loop           [ receive (realtime) -> fill UDP packet -> send  ]

 

 i think i need to implement a buffer ( FIFO or something) to store a certain number of samples so i wont lose samples in the transmision loop.

Any ideas of how implementing a FIFO driven by an external vhdl block (my I2S receiver ) but that i  easily could access from microblaze ? 

 

 

thanks to everybody and thanks to @PhDev , @zygot , @D@n , @xc6lx45 for replying my last question ? 

 

[jpeyron]

Hi @raultricking,

Here is the AXI4-Stream FIFO v4.1 LogiCORE IP Product Guide. The axi4 streaming FIFO ip core has an IP Example design available by right clicking on the IP Core that should be helpful.

thank you,

Jon