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daryon

Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !

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Dear all,

 

I am working with Vivado 2017.2 targeting a ZC706 ZYNQ FPGA Board operating on an Ubuntu 16.4 Linux Machine.

 

Previously targeting a Kintex-7 KC705 Board, I was able to choose the PCIe_refclk as the input clock of the buffer in vivadoblock design and use it as the clock signal in my design. Indeed, by double-clicking on the Utility Buffer IP, I had the option to connect the CLK_IN_D pin of the buffer to the PCIe clock.

 

Recently, I have migrated to ZC706 which includes a XC7Z045FPGA. While this FPGa has the PCIe and GTx channel, I do not see the PCIe_ref_clk available in the board file (board options) and also the  lspci command in terminal does not ercognize the ZC706 board while it is connected to the motherboard's PCI bus and also the system was restarted!

 

I also verified these links (link1, link2, link3) and found nothing helpful!

Did anyone experience this problem before to help me to solve this issue?

 

Thanks,

Daryon,

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Hi!

Check page 45 in https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf

It stated:

N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1)
N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1)

So just create clock input pins in your block diagram with any names.

After that define constraints in xdc file which connects your clk names to N7/N8 pins.

 

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On 10/11/2018 at 9:16 AM, ululuk said:

Hi!

Check page 45 in https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf write my essay

It stated:

N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1)
N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1)

So just create clock input pins in your block diagram with any names.

After that define constraints in xdc file which connects your clk names to N7/N8 pins.

 

Thank you for the information. Haven't been able to find this by myself, unfortunately.

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