I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning:
[Timing 38-282] The design failed to meet the timing requirements.
According to the Timing Report this warning refers to the Path from "hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C" to "hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D"
with source clock mmcm_clkout1 and destination clock dvi2rgb_0_PixelClk. The reported slack is -0.787.
Any timing constraints of this should have been provided by Vivado automatically, so what could I do about this warning?
I tried this on three different machines, always getting the same critical warning.
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effisio
Hello,
I downloaded the latest release of the "Nexys Video HDMI Demo" from Github (Nexys-Video-HDMI-2016.4-2.zip) and I installed Vivado 2016.4 only for the purpose of implementing the hardware design and generating the bitstream of this demo. I generated the project by executing the tcl-script in the proj-folder and then generated the bitstream. The write_bitstream was completed successfully but for the implemented design Vivado reported one critical warning:
[Timing 38-282] The design failed to meet the timing requirements.
According to the Timing Report this warning refers to the Path from "hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C" to "hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D"
with source clock mmcm_clkout1 and destination clock dvi2rgb_0_PixelClk. The reported slack is -0.787.
Any timing constraints of this should have been provided by Vivado automatically, so what could I do about this warning?
I tried this on three different machines, always getting the same critical warning.
Eff
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