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Timing constraints are not met.


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To solve a timing problem, you need to dig into the timing report. From your screenshot, we can see there are failing intra-clock timing constraints on clk_fpga_0. In order to resolve the failures, you need to look at what paths are failing.

You posted the .rpx file but it's easier to look at the report outside Vivado.

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is it possible that this block isn't meant to be used at 100 MHz?

There are 27 levels of logic, the signal needs 18 ns through the transistors alone plus another 15 ns for routing delay. The design demands the signal to be ready after 10 ns...

I may be wrong, observing from the distance, but this looks like a typical beginner mistake in the "IP block" (if this is 3rd party, non-Xilinx): Leave sufficient registers = delay in any non-critical path. Done consistently, it will also speed up P&R tremendously - the  job gets so much easier.
If it were an output from the IP block, you could fix the situation by running the output through a chain of ~ 5 registers, and turning register rebalancing on in the options.

But, I suspect, this was tested with a lower-frequency clock (e.g. 12 MHz from USB is popular)

 

 

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I have just come across the same problem as @greedyhao and was wondering if anyone else has. The tutorial involves using IP generated from the Matlab HDL coder in a previous tutorial, but they also provide the packaged IP for those, like me, who don't have access to Matlab. I'm using Vivado/Vitis 2020.1 and the tutorial uses software from 2015 so it took a bit of effort to get things to work at, e.g. port names were different from those in the provided constraints file and the IP Makefiles didn't work, but everything built in the end.

In fact, the whole thing runs on the Zedboard but the noise cancellation (the LMS filter) doesn't work. The system is supposed to take audio input, add tonal noise, perform noise cancellation and output the resulting audio. You can switch the output between original input, input + noise and the filtered signal but the filtered signal is the same as the noisy signal. The timing problems seem to be something to do with updating the adaptive filter's weights and I guess the filter has no effect because the weights never get updated but I don't really know.

It may not be possible to fix it easily as the IP was provided with the tutorial but it would be nice to understand what's gone wrong. However, as a complete beginner I don't have a clue where to start so I'd be grateful for any advice.

Thanks

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