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armin

Connecting HC05 bluetooth module to Arty 7 board

Question

Hey Guys,

 

Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors):

set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}];
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}];

about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow:

I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why?

here is the VHDL code (as I stated serial interface module works properly with USB port):

library ieee;

use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;



entity main is
    port(   CLK             :   in  std_logic;
            
            UART_TX         :   out std_logic;
            UART_RX         :   in  std_logic;

            BLUE_LED        :   out std_logic_vector(3 downto 0);
            GREEN_LED       :   out std_logic_vector(3 downto 0);
            RED_LED         :   out std_logic_vector(3 downto 0);
            LED             :   out std_logic_vector(3 downto 0)
    );
    end entity;
    
    
architecture behaviour of main is



    component uart is
    port (CLK               :   in std_logic;
          UART_RXD          :   in std_logic;
          UART_DATA_READ    :   out std_LOGIC_VECTOR(7 downto 0);
          UART_READ_FLAG    :   out std_logic;
          UART_DATA_WRITE   :   IN STD_LOGIC_VECTOR(7 downto 0);
          response_is_ready :   in std_logic;
          UART_TXD          :   out std_logic

      );
    end component;
    
    signal clock                :    std_logic;
    signal  data_send           :    std_logic_vector(7 downto 0);
    signal data_receive         :    std_logic_vector(7 downto 0);
    signal data_ready_to_send   :    std_logic;
    signal data_received        :    std_logic;
    signal LED_VALUE            :    std_logic_vector(3 downto 0);
    signal UART_RX_S            :    std_logic:='0';
    signal UART_TX_S            :    std_logic:='0';
    signal i_int                :    integer:=0;
    type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT);
    signal LED_STATE : LED_STATUS := INIT;



begin

    inst_UART:uart
    port map(               CLK                 =>      CLK,
                            UART_RXD            =>      UART_RX_S,
                            UART_TXD            =>      UART_TX_S,
                            UART_DATA_READ      =>      DATA_Receive,
                            UART_DATA_WRITE     =>      DATA_Send,
                            response_is_ready   =>      data_ready_to_send
                            );
    inst_proc:process(clk,DATA_Receive,LED_STATE)
    --variable i: integer:=0;
    begin
          
          
            if(rising_edge(clock)) then
                    GREEN_LED<=DATA_Receive(3 downto 0);
                    LED_VALUE<=DATA_Receive(7 downto 4);
                    

                                        
                                        
            end if;
    
    end process;
CLOCK<=CLK;
LED<=LED_VALUE;
UART_TX<=UART_TX_S;
UART_RX_S<=UART_RX;

end architecture;

Thx

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5 answers to this question

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Hi @armin,

We do not have an HC05 module. We do have some VHDL code in the Nexsys-3 PmodBT2 Demo that works with and older board in ISE and our PmodBT2 that should be helpful for at least the tx portion with uart. We do also have a IP core for the PmodBT2 and the PmodBLE  here that you could potentially alter to use with the HC05 and Microblaze.

thank you,

Jon

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Thanx for reply.

I consider the answer as an alternative standard solution.Lets forget for a while bluetooth issue, I am asuming TX RX ports does not work properly. I am wondering  whether we can set two other IO pins (except pins that are used for UART port on ARTY board) as TX and RX ?

here in my design, I used the following port as TX and RX ports. My uestion is whether these ports really works properly as TX and RX? or extra hardware should be assigned.

On 10/4/2018 at 7:05 PM, armin said:

set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}];

If they need further hardware module how can I implement it?

Thanks

Armin

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Hi @armin,

The pins E15 and E16 on the Pmod Port JB should work just fine for TX and RX. I would first program the Arty A7 using the TX and RX as E15, and E16 pins and then scope E15 and E16.  Are you able to see a UART signal?

thank you,

Jon

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Sorry I didnt get the procedure, I have  a UART port on board which I use for programming the FPGA.then in this case, you mean program the FPGA via these 2 ports?(e.g., via a converter?)Please let me know what you mean exaclty

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Hi @armin,

Sorry for the confusion. I am suggesting that you program your Arty-A7 as you would normally through the usb uart. The program on the Arty-A7 should be a UART controller using pin E15 and E16 on Pmod Port JB for the TX and RX of the project.

cheers,

Jon

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