Implementation Problem in vivado 2017.4

[ATIF JAVED]

Hello all of you hope you are in a good health

I converted my one of the project from vivado 2015.4 to 2017.4 . After changes i successfully synthesize my code but in implementation it give me this type of error(cal_val_inferred_i_1/O[3]  to a signal or tied to VCC or GND ) . After analysis i found out that this error is due to less usage of my bits as One of my wire have 20 bits but i only utilized its lower 9 bits . I declare one dummy register and assign this wire on that register but problem is still not resolved

 

Any kind of help in this regard is appreciable .

 

Best,

ATIF JAVED 

[BogdanVanca]

Hello @ATIF JAVED,

 

You don't have to create a dummy register in order to do some truncation. I don't have a lot of experience in verilog, but in vhdl you can simply assign the lower bits of a vector in this way:

signal a : std_logic_vector(3 downto 0);

siganal b: std_logic_vector(7 downto 0);

a <=  b(3 downto 0);

Best Regards,

Bogdan Vanca