XADC vivado simulation

[Newbiee]

I just found out that we can auto generate testbench using the 

tclapp::xilinx::designutils::write_ip_integrator_testbench -addToProject

I did successfully.

my block diagram is here

But I have the  input given in form of analog sim file and its included in the simulation sources, but I see something like this 

 

 

 

any inputs is appreciated.

 

 

Thanks.

[jpeyron]

Hi @Newbiee,

Please attach your testbench. Also are you giving the signals an initial value on startup in your testbench? 

thank you,

Jon

[Newbiee]

Hi @jpeyron,

 

I just succeeded partly but still not sure its working right. I have attached the tb here. 

I can see the clock running now. But the eoc that is automatically sending high signal is not seen.. (i have seen ILA debugger that without actually giving inpts to vn vp there are eoc automatically coming out after equal interval, assuming the same here).

XADC_test_tb.vhd

design_1_wrapper.vhd

[Newbiee]

Hi @jpeyron ,

 

Here is my another attempt. 

library IEEE;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;

entity test_design_1 is 
end test_design_1;


architecture TB of test_design_1 is

component design_1 is
port (
  dclk_in : in STD_LOGIC;
  eoc_out : out STD_LOGIC;
  vn_in : in STD_LOGIC;
  vp_in : in STD_LOGIC
);
end component design_1;

signal dclk_in : STD_LOGIC;
signal eoc_out : STD_LOGIC;
signal vn_in : STD_LOGIC;
signal vp_in : STD_LOGIC;    
begin
DUT: component design_1 port map (
        dclk_in => dclk_in,
        eoc_out => eoc_out,
        vn_in => vn_in,
        vp_in => vp_in
        );    
process
variable value_SPACE : character;
variable read_col_from_input_buf : line;
variable value_TIME, value_VP, value_VN : integer;
file input_buf : text;

begin 
    file_open(input_buf, "design.txt", read_mode);
          while not endfile(input_buf) loop
            readline(input_buf, read_col_from_input_buf);
            read(read_col_from_input_buf, value_TIME);
            read(read_col_from_input_buf, value_SPACE);           -- read in the space character
            read(read_col_from_input_buf, value_VP);
            read(read_col_from_input_buf, value_SPACE);           -- read in the space character
            read(read_col_from_input_buf, value_VN); 
            dclk_in <= std_logic_vector(to_unsigned(value_TIME, dclk_in'LENGTH));
            vn_in <= std_logic_vector(to_unsigned(value_VN, vn_in'LENGTH));
            vp_in <= std_logic_vector(to_unsigned(value_VP, vp_in'LENGTH));
          end loop;
          end process;
end TB;

For the same block design but without the input for den just using eoc as output. Kindly help me.

Its been a while but I am still stuck at this spot.

Thanks in advance.

[jpeyron]

Hi @Newbiee,

I do not have a lot of experience using the event driven mode in the XADC or the corresponding  XADC testbench. I do know that you can use the XADC IP example provided by xilinx. You'll need to highlight the XADC IP and right click on it, then select open ip example design. The example has a testbench as well.

thank you,

Jon

 

[Newbiee]

Hi @jpeyron, 

 

The thing is the testbench is in verilog, I have no knowledge of it.. it very difficult for me to get it so quickly, can you Tag anyone else atleast may be who can help me? It very important for me, kindly help me.

 

 

Thank you.

[jpeyron]

Hi @Newbiee,

I did find a thread that has a VHDL testbench here. Unfortunately,  those of us here at Digilent don't have the appropriate experience to answer your question. I would suggest to reach out to Xilinx support.

thank you,

Jon

[Newbiee]

But that's verilog isn't it? Or is that in vhdl? ?

[jpeyron]

Hi @Newbiee,

You are correct. I miss read what i  wrote in the linked thread above. I did find an xadc project  for the Basys 3 done by one of our community members @hamster that has a VHDL testbench that you can use as a reference here.

cheers,

Jon