I've created this simple mod16 counter using basys3 board and something is not right with my clock. The code itself do works, however one count (changing from "1" to "2" etc.) last 40 seconds, instead of 1 second! I've tried to lower the "clk_vector" if condition to 1 but it didn't help either.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mod_16_k is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (15 downto 0));
end mod_16_k;
architecture Behavioral of mod_16_k is
signal clk_vector :integer;
signal clk_vec2 :std_logic_vector(15 downto 0);
begin
zegar_wew : process(clk)
begin
if(clk'event and clk = '1') then
clk_vector <= clk_vector + 1;
if(clk_vector = 100000000) then
clk_vec2 <= std_logic_vector(unsigned(clk_vec2) + 1);
end if;
end if;
end process;
led <= clk_vec2;
end Behavioral;
If we check the basys3 datasheet, the clock is connected to "W5" port.:
Do you have any idea, what might be the problem in here? It might be connected with detecting the rising edge of an clk, however all of the changes (from 1 to 2 etc.) last ~40 seconds.
Question
donwazonesko
I've created this simple mod16 counter using basys3 board and something is not right with my clock. The code itself do works, however one count (changing from "1" to "2" etc.) last 40 seconds, instead of 1 second! I've tried to lower the "clk_vector" if condition to 1 but it didn't help either.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity mod_16_k is Port ( sw : in STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0)); end mod_16_k; architecture Behavioral of mod_16_k is signal clk_vector :integer; signal clk_vec2 :std_logic_vector(15 downto 0); begin zegar_wew : process(clk) begin if(clk'event and clk = '1') then clk_vector <= clk_vector + 1; if(clk_vector = 100000000) then clk_vec2 <= std_logic_vector(unsigned(clk_vec2) + 1); end if; end if; end process; led <= clk_vec2; end Behavioral;The .XDC lines for clock are:
set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]If we check the basys3 datasheet, the clock is connected to "W5" port.:
Do you have any idea, what might be the problem in here? It might be connected with detecting the rising edge of an clk, however all of the changes (from 1 to 2 etc.) last ~40 seconds.
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