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Venkat

Genesys2 demo project - not able to regenerate bit file

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Hi ,

I have purchased recently Genesys2 FPGA Board and trying to re generate the bit file OOB project.

I have followed the below steps mentioned in the Genesys 2 Out of Box Demo Tutorial:

1. Downloaded the project.

2. Installed the Vivado board file for Genesys2

3. Generated OOB project by sourcing the tcl script in Vivado.

When tried to to Genearate bitstream I get the following error:

image.png.12179f684aeb3e860573ca49acc80c11.png

 

Also when tried to synthesize I am getting the following error:

image.png.b1a59cbf03cc5ba458844b58872a3229.png

 

Looks like there are no source files present in the project repository.


Where to get the Genesys2 OOB Project source files ?

 

Appreciate for your time and help.

 

Regards,

Venkat

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Hello @Venkat,

What version of Vivado do you use ?  I'm asking this because tcl. scripts are extremely version specific. For example the script that creates the Out of the Box demo for Genesys2 will work only with Vivado 2015.4. Additionally, what edition of Vivado are you using? The free WebPACK edition will not be able to generate a bitstream for any Genesys 2 projects since it's chip is not supported in WebPACK.

Best Regards,

Bogdan Vanca 

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Hi @Venkat,

Neither of the release out of the box demos for the Genesys 2 are designed to work with Vivado 2018.2, so the script as is would not work. Additionally, do you have the free WebPACK version of Vivado or do you have the Design Edition of Vivado? In the interest of being fully transparent, we also found an unrelated error with one of the releases that we are working on fixing as well.

Thanks,
JColvin

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13 hours ago, BogdanVanca said:

 I'm asking this because tcl. scripts are extremely version specific.

You've probably heard the old saw that one definition of insanity is trying to do the same thing over and over ( for years and years maybe... ) and expecting different results. I guess some people at Digilent need to prove that there might be merit to the idea.  For years I've been trying to push, sometimes gently, and sometimes not so much, the idea that there's a better way to handle the "Xilinx IP project flow", if one HAS to; but that there are better ways to do things to help customers with their brand new hardware that they want to see doing something useful.

For a board like the Genesys2, where the customer is required to have at least a node-locked licence to even create a bitstream, insisting that customers use a specific version of Vivado to suit the mess that Digilent has created for itself is just plain outrageous, on the road to almost 'criminal'. I've gotten quite a bit of use for my Genesys2 board and have never tried to create a bitstream from a Digilent demo project. The board is great. The support is, well... not that.

Unfortunately, by pushing the decision makers at Digilent to make their lives better as well as the lives of their customers I'm almost certainly guaranteeing that it will never happen. But I'll try again ( hopefully, you've already forgotten the first line of this post... )

  • You can post designs that are a lot friendlier to Vivado version rot if you do your homework and use a bit of intelligence. I don't use this flow except in the least painful way possible, but I've seen it done elsewhere.
  • Everyone will be happier if you just write your own IP to make your FPGA boards functional. At the end of the day it will also be cheaper and make for happier customers... even student customers deserve a little happiness.

Call me crazy ( I think that I already did ) but when someone publicly offers you good advice it seems prudent to either offer a good reason for not taking it, having a quality private discussion, or just admit that you really couldn't be bothered.

PS. Yesterday, I built a Xilinx project for their ZCU106. I used Vivado 2018.2.1 and the project was built in Vivado 2018.1. This was the first time that I've ever created a bitsream AND ARM code that worked on the first try ( actually, I had to make a minor edit to one batch file ) while using a newer version of Vivado than the project was created in. The first time that's happened since Vivado was released! I'm still in shock.

 

Edited by zygot

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Hi @JColvin,

I am using Vivado Design Edition.

I agree with @zygot, that the demo design need to be free from tool version.

If this is tool specific, then why not Digilent provides the Source Code for the Demo board itself.?

Is there a way for you or someone @ Digilent to run the Demo with Vivado 2015.4 and provide the Source Code as attachment here.

I believe I have seen a thread mentioning about the Source Code Zip file attachment, somehow I couldn't see it.

Regards,
Venkat

 

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Hi @Venkat,

If the projects were in HDL (VHDL/Verilog) then this would not be an issue. When using Microblaze and IP Cores the version matters. At this time we have not found a feasible way to convert the MicroBlaze and IP core portions of the OOB to HDL in order to reasonable resolve the version issue. I will pass your request on to our content team.  I believe when getting the design Edition you should also be able to download and use earlier versions of Vivado/SDK Design edition like Vivado/SDK 20015.4 for the term of your license. You should be able to run the HDL Genesys 2 OLED and Keyboard demos here in the newer version of Vivado design edition.

thank you,

Jon   

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3 hours ago, jpeyron said:

I believe when getting the design Edition you should also be able to download and use earlier versions of Vivado/SDK Design edition like Vivado/SDK 20015.4 for the term of your license

Node locked licenses are permanent though can only be used on one computer. The statement about using older versions of Vivado with a node-locked license might be correct though I haven't tested this. I have 3 licenses for 3 different boards with the same device as the Genesys2 has from 3 different years and frankly don't know which one is in the license file. The license file does have a start date embedded in it but I don't know if that poses restrictions on installing and using earlier versions of Vivado.

3 hours ago, jpeyron said:

If the projects were in HDL (VHDL/Verilog) then this would not be an issue. When using Microblaze and IP Cores the version matters

@jpeyron

Let me float a proposal. Provide small stipends or other ways of reimbursing third parties to develop IP for particular board interfaces. I'm sure that yo have employees who would be happy to develop their skills along these lines for a reasonable reimbursement. If not there are no doubt competent students or customers who would be willing to do that. Of course the deliverables would have to be shown to work and have proper testbenches. Obviously, this was done for the DPTI demo ( though no one seems to have actually tested it ). Put the code into a community forum. I'm sure that you will find that there are people willing to contribute to the improvement of the code. The only thing guaranteeing failure is never getting started.

Ethernet connectivity has always been an area that Altera and Xilinx have wanted to preserve as paid IP. There is simply no justification for that. You don't need to supply a full TCP/IP stack to demonstrate that the interfaces work. There is already free HDL project code submitted to the Project Vault to provide minimal Ethernet connectivity. A number of people have contributed free stuff to Digilent... perhaps trying to reciprocate might benefit everyone, particularly Digilent. At least consider it.

The biggest problem, as you know, with Vivado version rot is that it's not usually a few hours of work to fix issues but days of work often, for me, ending up being abandoned because I had other priorities ( I haven't even tried using a demo from Digilent for a few years now and Digilent and I are almost always out of sync with versions. This is particularly true when using MicroBlaze and the SDK. You can make hardware demos that are better than the ones available for the Genesys2 without a soft processor. Since you reuse hardware interfaces we're not talking about an infinity large problem. The nice thing is that once you have some core IP that's been around for a while and improved by your customer base your workload can be streamlined and  eased considerably. I understand that maintaining such an effort takes some amount of commitment on your part. But Digilent has, in the past, done this in some fashion for various add-on products.

Lastly, I'll point out that many of your customers, particularly in the USA where the internet ( and the laws governing it and the federal agencies who are supposed guard it )  is controlled by cartels, don't have access to broadband. The last time I had to download Vivado it was 22GB and took over 2 weeks of repeated failure ( including assistance from Xilinx ) to successfully obtain the installation files. That's pretty ridiculous. Doing that for 4-5 version of Vivado just to compile a demo is more than unreasonable.

 

Edited by zygot

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Hi @zygot,

I was going off of this AR from xilinx about older vivado version. It states that the license will enable any version of the design tools released during or before the month specified by the Version Limit.  We will forward your suggestions to our content team as well as our management. 

thank you,

Jon

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