The E9 pin of xc7a100tcsg324-1

[sieg70]

hi,

I want to porting a project from Arty (Artix-7 xc7a35tcsg324-1 ) to the Nexys4-ddr (xc7a100tcsg324-1).
The design use the QSPI NOR flash as the storage, so it assigns the SCK to the L16 in Arty board.

My question is, when I use Nexys4-ddr and assign the SCK to pin E9, but E9 is a dedicated configuration pin.
Although I wrote the rules in xdc, I got such message as following:

[Common 17-69] Command failed: 'E9' is not a valid site or package pin name. ["C:/lab/test/test.srcs/constrs_1/new/demo.xdc":5]

How could I use the E9 pin in my FPGA design to control the NOR flash?

[jpeyron]

Hi @sieg70,

I believe that the Nexys 4 DDR's flash/FPGA was wired differently than the Arty. Looking at the Arty schematics L16 is QSPI_SCK and connected to IO_L3N_T0_DQS_EMCCLK_14 on IC1F and in the Nexys 4 DDR L16 is tied to SW1 as well as the IO_L3N_T0_DQS_EMCCLK_14 on IC8F. I do not think that this function was implemented in the Nexys 4 DDR so i do not know if you would be able to use the FLASH in the same way as you do on the Arty. You could try to tie a clock set to the same frequency as was used in your Arty project to L16 and see if it works the same.  Remember, during this project you would not be able to use SW1.

thank you,

Jon

[PhDev]

Hi @sieg70

You can use the STARTUPE2 primitive to access E9.

STARTUPE2_i : STARTUPE2
    port map (
        CFGCLK => open,       -- 1-bit output: Configuration main clock output
        CFGMCLK => open,     -- 1-bit output: Configuration internal oscillator clock output
        EOS => open,             -- 1-bit output: Active high output signal indicating the End Of Startup.
        PREQ => open,           -- 1-bit output: PROGRAM request to fabric output
        CLK => '0',             -- 1-bit input: User start-up clock input
        GSR => '0',             -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
        GTS => '0',             -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
        KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
        PACK => '0',           -- 1-bit input: PROGRAM acknowledge input
        USRCCLKO => SPI_Clk,   -- 1-bit input: User CCLK input
        USRCCLKTS => '0',  -- 1-bit input: User CCLK 3-state enable input
        USRDONEO => '0',   -- 1-bit input: User DONE pin output control
        USRDONETS => '0'  -- 1-bit input: User DONE 3-state enable output
    );

With this SPI_Clk goes to E9.

[yildizabdullah]

On 9/21/2018 at 8:37 AM, PhDev said:

Hi @sieg70

You can use the STARTUPE2 primitive to access E9.

STARTUPE2_i : STARTUPE2
    port map (
        CFGCLK => open,       -- 1-bit output: Configuration main clock output
        CFGMCLK => open,     -- 1-bit output: Configuration internal oscillator clock output
        EOS => open,             -- 1-bit output: Active high output signal indicating the End Of Startup.
        PREQ => open,           -- 1-bit output: PROGRAM request to fabric output
        CLK => '0',             -- 1-bit input: User start-up clock input
        GSR => '0',             -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
        GTS => '0',             -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
        KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
        PACK => '0',           -- 1-bit input: PROGRAM acknowledge input
        USRCCLKO => SPI_Clk,   -- 1-bit input: User CCLK input
        USRCCLKTS => '0',  -- 1-bit input: User CCLK 3-state enable input
        USRDONEO => '0',   -- 1-bit input: User DONE pin output control
        USRDONETS => '0'  -- 1-bit input: User DONE 3-state enable output
    );

With this SPI_Clk goes to E9.

I get an error during Implement Design step in Xilinx ISE as 

ERROR:MapLib:30 - LOC constraint E9 on spi_clk is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

When I place a location constraint for spi_clk pin which is input to my top module.

 

[jpeyron]

Hi @yildizabdullah,

You will need to use the primitive as discussed in your other post here.

best regards,

Jon

[PhDev]

@yildizabdullah

spi_clk is an input to STARTUPE2 and can not have a loc constraint.

It will automatically be routed to E9.