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bklopp

Creating a Clocking Wizard with Differential Input via Board File?

Question

Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so.

A single-ended clock interface in the board.xml file looks like this:

      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset">
        <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
		<port_maps>
          <port_map logical_port="clk" physical_port="clk" dir="in">
            <pin_maps>
              <pin_map port_index="0" component_pin="clk"/> 
            </pin_maps>
          </port_map>
        </port_maps>
        <parameters>
          <parameter name="frequency" value="100000000" />
       </parameters>
      </interface>

Which allows one to click and drag "System Clock" from the board tab into the block design and gives you a clocking wizard with a single-ended clock.

image.png.31f02873ed775e9cbef9f1db9011af44.png

 

I want to be able to do the exact same thing, except instead of spawning a clocking wizard with a single-ended clock, it spawns a clocking wizard with a differential clock, like this:

image.png.f6eedb596fe093bed000857de0244c0e.png

Here is my failed attempt at creating this interface:

I used "xilinx.com:signal:diff_clock_rtl:1.0" instead of "xilinx.com:signal:clock_rtl:1.0" and added another port map for the p/n signals.

      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:diff_clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset">
        <description>3.3V Double-Ended 100MHz oscillator used as system clock on the board that don't work none good</description>
		<port_maps>
			<port_map logical_port="CLK_P" physical_port="clk_p" dir="in">
				<pin_maps>
				  <pin_map port_index="0" component_pin="clk_p"/> 
				</pin_maps>
			  </port_map>
			  <port_map logical_port="CLK_N" physical_port="clk_n" dir="in">
				<pin_maps>
				  <pin_map port_index="0" component_pin="clk_n"/> 
				</pin_maps>
			  </port_map>
			</port_maps>
        <parameters>
          <parameter name="frequency" value="100000000" />
       </parameters>
      </interface>

and I added the following pins to my pin file:

<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
<part_info part_name="xc7a200tffg1156-2">
<pins>
  <pin index="00" name ="clk_p"                        iostandard="LVCMOS25" loc="AG29"  />
  <pin index="01" name ="clk_n"                        iostandard="LVCMOS25" loc="AG30"  />

Which gives me this message: "'System Clock' board component cannot be connected because no possible options to connect."  when I try to click and drag system clock into the design:

image.png.1bd0ad89a2bd71cb0a270c8079ba7bd3.png

Do I need to edit the preset file, or is the syntax for my interface definition incorrect, or am I missing something else entirely?

Any help is greatly appreciated. 

Thanks in advance :)

 

Edited by bklopp
left some images in by accident

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3 answers to this question

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Hello @bklopp,

I don't have a lot of experience with scripts, but this is what Xilinx does for zcu102. See if it helps you :) . 

    <interface mode="slave" name="user_si570_sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="user_si570_sysclk">
          <parameters>
            <parameter name="frequency" value="300000000"/>
          </parameters>
          <preferred_ips>
            <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
          </preferred_ips>
          <port_maps>
            <port_map logical_port="CLK_P" physical_port="user_si570_sysclk_p" dir="in">
              <pin_maps>
                <pin_map port_index="0" component_pin="user_si570_sysclk_p"/>
              </pin_maps>
            </port_map>
            <port_map logical_port="CLK_N" physical_port="user_si570_sysclk_n" dir="in">
              <pin_maps>
                <pin_map port_index="0" component_pin="user_si570_sysclk_n"/>
              </pin_maps>
            </port_map>
          </port_maps>
        </interface>

Best Regards,

Bogdan Vanca 

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  • 0

Awesome, thanks guys that worked for me.

I also had to make sure the component definition name matched the "of_component=" name in the interface definition.

For anyone with the same problem, here is the working interface definition in the board.xml file:

<interface mode="slave" name="sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sysclk">
    <parameters>
      <parameter name="frequency" value="300000000"/>
    </parameters>
    <preferred_ips>
      <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
    </preferred_ips>
    <port_maps>
      <port_map logical_port="CLK_P" physical_port="sysclk_p" dir="in">
        <pin_maps>
          <pin_map port_index="0" component_pin="sysclk_p"/>
        </pin_maps>
      </port_map>
      <port_map logical_port="CLK_N" physical_port="sysclk_n" dir="in">
        <pin_maps>
          <pin_map port_index="0" component_pin="sysclk_n"/>
        </pin_maps>
      </port_map>
    </port_maps>
</interface>

And the working component definition in the board.xml file:

  <component name="sysclk" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
	<description>100 MHz Differential System Clock</description>
  </component>

And finally the pins in the pins file

<pins>
  <pin index="00" name ="sysclk_p"                    iostandard="LVCMOS25" loc="AG29"  />
  <pin index="01" name ="sysclk_n"                    iostandard="LVCMOS25" loc="AG30"  />
  ...

 

Edited by bklopp

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