Test Bench example for the following RAM code?

[TJ]

Hello,

Does anyone know of a good VHDL test bench reference for the following VHDL code?  Also, does my below RAM VHDL code make sense?

Thanks,

TJ

Pseudo Dual Port VHDL Example
library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 

entity daul_port_ram is 
generic (data_width : natural := 8; 
addr_width : natural := 16); 
port ( clk_in : in std_logic;
clk_out : in std_logic;
we, re : in std_logic;
addr_in : in std_logic_vector( addr_width - 1 downto 0);
addr_out : in std_logic_vector( addr_width - 1 downto 0);
data_in : in std_logic_vector( data_width - 1 downto 0);
data_out : out std_logic_vector( data_width - 1 downto 0)
); 
end daul_port_ram; 

architecture daul_port_ram_arch of daul_port_ram is 

type mem_type is array (2** addr_width downto 0) of std_logic_vector( data_width - 1 downto 0) ;
signal mem : mem_type ;

begin 

mem_write : process (clk_in, we) 
begin 
if clk_in'event and clk_in = '1' and we = '1' then 
mem( conv_integer( addr_in)) <= data_in ; 
end if ; 
end if ; 
end process write ; 

mem_read : process (clk_out, re) 
begin 
if clk_out'event and clk_out = '1' and re = '1' then 
data_out <= mem( conv_integer( addr_out)) ; 
end if ; 
end process read;

end daul_port_ram_arch;

[hamster]

Hi TJ

Your code is 99% of the way there. Here's the last 1% that I can see.

- I am not sure that you need "we" and "re" on your sensitivity list. I would reformat the code with nested 'if's. e.g.:

 

mem_read : process (clk_out) 
    begin 
        if clk_out'event and clk_out = '1' then
            if re = '1' then 
                data_out <= mem( conv_integer( addr_out)) ; 
            end if ; 
        end if ; 
end process read;

- There is a more subtle problem. As the read and write is split over two different processes, there is a bit of flexibility in which occurs first and which occurs second. I don't know the full semantics of this (do both processes get run, then the updates occur? or do they individually run and update, with flexibility as to who gets to run first). Seems to be a perfect place for some undefined behavior to occur, causing a simulation / synthesis miss-match. I would recommend that you fix this by putting everything in one process.

- You really want to initialize the contents of your memory array, otherwise simulation will not match what occurs in the FPGA.

signal mem : mem_type  := (others => (others => '0'));

 

[TJ]

Hello Hamster,

Thank you very much.  I agree the "re" and "we" does not need to be in sensitivity list.  I agree the read and write should be in same process.   Do you know of a test bench recommendations for this?

Thanks,

TJ

[hamster]

3 hours ago, TJ said:

Hello Hamster,

Thank you very much.  I agree the "re" and "we" does not need to be in sensitivity list.  I agree the read and write should be in same process.   Do you know of a test bench recommendations for this?

Thanks,

TJ

If you suggest one, and we'll make it better together?

there is actually quiet a bit that could be tested. Writing & reading the same address at the same time, or reading the address the cycle after it is written,, with/without write enable set, does read enable work correctly...

Do you have any sort of a test plan drawn up, detailing what you want to test?

[TJ]

Hello hamster,  No test plan yet but when I do I will let you know if I have questions.  Thanks again.   I do have test bench set up reading and writing data using variables but not yet RAM.  Thanks again .