• 0
dfergenson

Zybo Z7-20 HDMI Demo Unimplementable As Posted

Question

I'm attempting to get the Zybo Z7 HDMI demo running on my Zybo Z7-20. I was able to get a bitstream generated from the Zybo Z7-10 version of the demo working without issue but not from the Zybo Z7-20.

I'm running Xilinx SDx version 2016.4.

I ran into and resolved some unrelated issues such as:

  1. I added the Digilent-specific IP.
  2. I dealt with an IP version issue.
  3. I specified the top level of the project as being the diagram itself.

After having done this, I've been able to synthesize and implement the project. But I could not generate a bitstream and the problem seems to be an incompatibility between the diagram as drawn and the board as described in the documentation which is specifically being raised as in issue in the XDC file.

Here is the specific error that I get:

Quote

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 12 out of 159 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_out_ddc_scl_i, hdmi_out_ddc_scl_o, hdmi_out_ddc_scl_t, hdmi_out_ddc_sda_i, hdmi_out_ddc_sda_o, hdmi_out_ddc_sda_t, hdmi_in_ddc_scl_i, hdmi_in_ddc_scl_o, hdmi_in_ddc_scl_t, hdmi_in_ddc_sda_i, hdmi_in_ddc_sda_o, hdmi_in_ddc_sda_t.

This seems like it should be a fairly simple problem to work around but I've been unable to determine how to do so.

But perhaps I'm missing something very obvious?

So, my concrete questions are:

1. Has anyone successfully gotten the Zybo Z7-20 version of the HDMI example to synthesize "out of the box"?

2. Does anyone have an edited version of the .XDC for the Zybo Z7 that has been made to work?

Otherwise, I'll reply to this post with a working .XDC if I'm able to get it working.

I've attached the default .XDC to this post just in case it helps.

Zybo-Z7-Master.xdc

Share this post


Link to post
Share on other sites

7 answers to this question

Recommended Posts

  • 1

Hi @dfergenson,

I was able to generate a bitstream with the Zybo-Z7-20 HDMI Demo in Vivado 2016.4 with out having to alter the xdc or board files. I would suggest to start with a freshly unzipped demo from here.  Load the project in Vivado by using the TCL console. Type CD [path yo proj folder of demo]. Then type source ./ and select create_project.tcl.  Once the project is loaded upgrade the IP's by using tools->reports->report ip status. Then right click on design in source tab and create a wrapper. Next select generate a bitstream.  Let us know if you are not able to generate a bitstream. To confirm you are using Vivado 2016.4 and your board is the Zybo-Z7-20?

thank you,

Jon

Share this post


Link to post
Share on other sites
  • 0

Hi @dfergenson,

A few of the IP Core were updated . The pin names were altered in the updated ip cores. The XDC pins listed in the error need to be altered to match the wrapper  :   hdmi_out_ddc_scl_i, hdmi_out_ddc_scl_o, hdmi_out_ddc_scl_t, hdmi_out_ddc_sda_i, hdmi_out_ddc_sda_o, hdmi_out_ddc_sda_t, hdmi_in_ddc_scl_i, hdmi_in_ddc_scl_o, hdmi_in_ddc_scl_t, hdmi_in_ddc_sda_i, hdmi_in_ddc_sda_o, hdmi_in_ddc_sda_t.

thank you,

Jon

Share this post


Link to post
Share on other sites
  • 0

Jon,

Thanks. After reviewing the Zybo Z7-10 version of the code and the specifications of both -10 and -20 PCBs and processors, I decided that the simplest route would just be to change the board definitions file in the -10 version to a Zybo Z7-20. As before, everything synthesized.

Can you see anything wrong with this approach?

-David

Share this post


Link to post
Share on other sites
  • 0

Thanks. I had downloaded the .zip from the link on the resources page. I did use Vivado 2016.4 and reconstituted the demo using the TCL command. Yes, I'm using a Zybo Z7-20, though I hadn't gotten far enough on the -20 demo for it to have come into play. I will run through the process again and will let you know how things go. -David

Share this post


Link to post
Share on other sites
  • 0

Thanks, Jon. I was able to synthesize and generate a bitstream and memory configuration file. I would like to note that the model of the memory is not explicitly described in the specifications and there are three models of Spansion memory that seem to fit that general description. Can the specifications be updated to reflect the actual memory module for configuration file generation?

I also think that I've determined the root cause of the problem.

In the -10 version of the example code, I think that all of the IP was already up to date. In the -20 version, the DVI2RGB version was 1.7 when the current version was 1.8. This hung up a critical step in the TCL script. I read through the logs and found the following error had been thrown:

Quote

[BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'design_1.bd' is locked. Locked reason(s):
* BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
design_1_dvi2rgb_1_0

So the out of date IP interfered with the creation of the top level wrapper (which you instructed me to create once I had updated the IP). That wrapper was created automatically in -10. What I had done instead was specify design1.bd as the top level file for synthesis. Vivado lets you do that if you type in the name but I now realize that, while permissible, it's not a good practice because it caused those ports not to be recognized when Vivado encountered them in the .XDC file.

So, if whoever maintains the Git could update that IP, that would permanently solve the problem.

Thanks again for your guidance. Adding the wrapper HDL was, indeed, the missing link.

-David

Share this post


Link to post
Share on other sites
  • 0

I don't know if I missed it earlier or if it was just added today but the flash memory part number is absolutely mentioned in the Zybo Z7 specifications. It is a Spansion S25FL128S. Either thank you very much or else sorry to have bothered you.

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now