I'm attempting to get the Zybo Z7 HDMI demo running on my Zybo Z7-20. I was able to get a bitstream generated from the Zybo Z7-10 version of the demo working without issue but not from the Zybo Z7-20.
I'm running Xilinx SDx version 2016.4.
I ran into and resolved some unrelated issues such as:
I added the Digilent-specific IP.
I dealt with an IP version issue.
I specified the top level of the project as being the diagram itself.
After having done this, I've been able to synthesize and implement the project. But I could not generate a bitstream and the problem seems to be an incompatibility between the diagram as drawn and the board as described in the documentation which is specifically being raised as in issue in the XDC file.
Here is the specific error that I get:
Quote
[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 12 out of 159 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_out_ddc_scl_i, hdmi_out_ddc_scl_o, hdmi_out_ddc_scl_t, hdmi_out_ddc_sda_i, hdmi_out_ddc_sda_o, hdmi_out_ddc_sda_t, hdmi_in_ddc_scl_i, hdmi_in_ddc_scl_o, hdmi_in_ddc_scl_t, hdmi_in_ddc_sda_i, hdmi_in_ddc_sda_o, hdmi_in_ddc_sda_t.
This seems like it should be a fairly simple problem to work around but I've been unable to determine how to do so.
But perhaps I'm missing something very obvious?
So, my concrete questions are:
1. Has anyone successfully gotten the Zybo Z7-20 version of the HDMI example to synthesize "out of the box"?
2. Does anyone have an edited version of the .XDC for the Zybo Z7 that has been made to work?
Otherwise, I'll reply to this post with a working .XDC if I'm able to get it working.
I've attached the default .XDC to this post just in case it helps.
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dfergenson
I'm attempting to get the Zybo Z7 HDMI demo running on my Zybo Z7-20. I was able to get a bitstream generated from the Zybo Z7-10 version of the demo working without issue but not from the Zybo Z7-20.
I'm running Xilinx SDx version 2016.4.
I ran into and resolved some unrelated issues such as:
After having done this, I've been able to synthesize and implement the project. But I could not generate a bitstream and the problem seems to be an incompatibility between the diagram as drawn and the board as described in the documentation which is specifically being raised as in issue in the XDC file.
Here is the specific error that I get:
This seems like it should be a fairly simple problem to work around but I've been unable to determine how to do so.
But perhaps I'm missing something very obvious?
So, my concrete questions are:
1. Has anyone successfully gotten the Zybo Z7-20 version of the HDMI example to synthesize "out of the box"?
2. Does anyone have an edited version of the .XDC for the Zybo Z7 that has been made to work?
Otherwise, I'll reply to this post with a working .XDC if I'm able to get it working.
I've attached the default .XDC to this post just in case it helps.
Zybo-Z7-Master.xdc
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