Simple Dual Port BRAM

[newkid_old]

Can someone give some advice on the workings of the Simple Dual Port BRAM?  I'm using channel A to store data thats coming from my ADC and channel B to read into my Microblaze processor.  On the first pass it works (I verify by means of a known value coming out of the ADC) but subsequent passes the BRAM doesn't seem to read the new values coming out of the ADC.  I've included a screenshot of how the BRAM is hooked up.  I'm using an AXI GPIO to toggle the (Read/Write) pin on the BRAM as well as the address generator.   I've also included my SDK program.  Any help is appreciated.

 

Cheers,

Curt

BRAM_Synch.txt

[BogdanVanca]

Hello @newkid_old,

Please check the fallowing links: 

1. https://www.youtube.com/watch?v=gfpE81yMBwQ&t=218s

2. https://www.youtube.com/watch?v=SGvYkA87W20

The first link is a tutorial that teach you how to correctly instantiate an BRAM ip-core. And the second one shows you how to create a test-bench for it (a simple write and read operation).

In my opinion it would be much easier for you, an much faster, to create your own BRAM ip-core. And that is because, an BRAM is nothing more than an array of arrays. In VHDL it will look something like this  : ""type BRAM is array (0 to 2**AddrBits - 1) of std_logic_vector(RAM_Width-1 downto 0);" where AddrBits and  RAM_Width are constants that defines the size of your  BRAM.

The process of reading and write are done "simultaneous" into an single process. Something like this :
 

       "ram_process: process (clk)
       begin
          if Rising_Edge(clk) then
             if (We = '1') then                   -- when you want to write into you BRAM.  
                BRAM(Addr) <= data_in; -- you store the input data on a given address.
             end if;
           data_out <= BRAM(Addr);    -- after writing, you output your data.
          end if;
       end process ram_process;"

After you test your top module, you can make your own ip-core, and finally add it to your block design. 

Best Regards,

Bogdan Vanca

 

 

[Notarobot]

Hi newkid_old,

It is difficult to diagnoze your problem since the diagram is not complete and it is not clear what is the FPGA code. I assume that BRAM is used by both FPGA logic and Microblaze.

Anyway, I would make two notes:

1. The signal wea should be either 8-bit or 4-bit depending your your BRAM configuration.

2. If you write to one port and read from the second you don't need to toggle wea or check it when writing. It can be set once only. Both ports A and B are independent. Make sure that in properties you set write_first for port A and read_first for port B.

Since you are using Vivado block design no instantiation of BRAM is needed in the HDL code. It is very easy but for the price of very limited configuration options. It works for me though.

Highly recommend to create and run workbench BRAM simulation. BTW, Vivado has help with RAM coding examples explaning proper usage.

[newkid_old]

Thanks for the information.  I will give it a try.

 

Cheers,

Curt