io timing constraints for pmod sf3 and arty s7

[addNameHere]

I have an sf3 connected onto an arty s7.  The timing report from Vivado tells me that I am missing constraints on the spi interface.  Are there any io timing constraints available for pmods?   

[jpeyron]

Hi @addNameHere,

If you havent already please install the board files here.  Are you using the Getting Started with Digilent Pmod IPs tutorial? Here is the Vivado library which includes an IP Core for the Pmod SF3. Are you connecting  the IP's ext_spi_clk port to a 50 MHz clock. The QSPI_INTERRUPT pin needs to be connected to an interrupt controller.  

thank you,

Jon

[addNameHere]

I think I found what I was looking for - in the PmodSF3_axi_quad_spi_0_0.xdc.  However, all of the constraints are commented out with a comment that the user should uncomment based on board delays and use - aren't these constraints specifically for the board/pmod already?

Thanks,

Dave

[jpeyron]

Hi @addNameHere,

Could you post you vivado block design and your wrapper and xdc file.

thank you,

Jon