Can't get reVISION-Zybo-Z7-20 to work

[chhsieh0309]

Hi there, I was trying the reVISION-Zybo-Z7-20 project on github but failed to get it to work. Here are what I do:

1. Download reVISION-Zybo-Z7-20 from Digilent github

git clone --recursive https://github.com/Digilent/reVISION-Zybo-Z7-20.git

2. Starting Vivado and generating block design without any change

Then I encounter the following error messages:

[Synth 8-439] module 'zybo_z7_20_v_frmbuf_wr_0_0_v_frmbuf_wr' not found [zybo_z7_20_v_frmbuf_wr_0_0.v:267]
[Synth 8-285] failed synthesizing module 'zybo_z7_20_v_frmbuf_wr_0_0' ["zybo_z7_20_v_frmbuf_wr_0_0.v:58]
 

The Video Frame Buffer Write component synthesis report shows that the root cause is "Parameter C_M_AXI_MM_VIDEO_DATA_WIDTH bound to: 32" which is set to 64 in block design. That makes me confused. I've downloaded the Zybo Z7-20 Base Linux Design and can generate bitstream file without any error.

report.txt

[jpeyron]

Hi @chhsieh0309,

In the readme for the reVISION Zybo-Z7-20 there are some known issues.  

#1. In the Vivado block diagram, typically the processing system IP core will infer a BUFG on the FCLK signals. For some reason, this is occuring for FCLK0 only. FCLK2 seems to be getting a BUFG added during implementation, so it doesn't cause any issues for that net, but FCLK 1 was being routed as a normal signal (not on the global clock network). This caused insanely long build times and failure to meet timing. The current work around is to manually insert a BUFG on FCLK1 using a util_ds_buf IP core.

I believe this is the issue you are experiencing.

thank you,

Jon