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On and off-chip connections with EMIO GPIO


I'm working with a CORA Z7 board and developing a system that will use make on and off-chip connections for the GPIO interface via the EMIO.  A conceptual block diagram of what I am trying to put together is shown below:


I will have a 16-bit wide constant IP block in PL that holds version information to be read-only as seen by the PS, along with a 2-bit wide pair of lines from the push buttons, and finally a 6-bit wide group of outputs to drive the LEDs.

My (working, now) solution involves a concat and a slice block in addition to the constant and processor subsystem blocks:


Does this seem like an overly-complicated approach, or is this the only way to avoid Vivado throwing errors because the 18-bit wide input and 6-bit wide output don't match the 24-bit wide GPIO_I and GPIO_O ports respectively?

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Thanks for the input.  I suppose the VHDL or Verilog approach would require a little more design-entry work overall on my part, but would make the block diagram a little bit cleaner and easier to follow.  For this project, I don't think it makes sense to go down that path, but in the future if I need to add some VHDL/Verilog-defined modules anyway, then I'd want to do this.

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