Default Power-up Value of Registers

[Foisal Ahmed]

I am using Vivado 2015 tools for Basys 3 FPGA Board. I want to fix all of the Register into default Logic state 1. Where and how can I do this? In the Tools or XDC file. Please kindly solve this problem. Thanks for advance.

Regards

Foisal Ahmed

[BogdanVanca]

Hello @Foisal Ahmed,

What registers ? Can you please be more specific ? Thank you.

Best Regards,

Bogdan Vanca 

[Foisal Ahmed]

Thanks, BogdanVanca for your reply. 

The default initial state for all registers, LUT and latches are zero (Logic state 0). Before downloading the specific Verilog file on the FPGA, I want to force the initial value of all LUTs as  1 (logic state ) instead of the default 0 value. So, Where and how I can do this. Please help to solve the Problem.

Thanks

[D@n]

@Foisal Ahmed,

I'm not sure you understand what you are asking.

1. Uninitialized logic values in Xilinx designs are already 1'b1's.  This has caused me no end of grief in the past.
2. Simulations treat initial values differently.  Most simulations will treat an uninitialized value as an unknown until it is set.  This is industry practice.  I know Verilator tries to set unconstrained initial values to be random numbers.  This is an exception to the industry practice that is done for performance reasons.  The discrepancy between Verilator and Xilinx has been the root of much grief--since uninitialized things that work in Verilator don't always work in Xilinx.
3. Depending upon a default initial value for registers within a design, however, is poor practice.  The better approach is to force registers that need initial values to whatever initial value they should have.  In Verilog, this is done using an 'initial' statement.  In VHDL this can be done in the declaration statement, where the register is declared in the first place.
4. Xilinx FPGA's by design will not release your design from its initial state unless all of your registers have their declared initial values.
5. Were you to force all LUTs in a design to be 1'b1 initially, you would break any vendor supplied IP (i.e. DDR3SDRAM core, etc) you might be working with.

Can you explain more of what you are trying to accomplish?  Perhaps there's a better solution for what you wish to do.

Dan

[Foisal Ahmed]

Dear D@n,

Thank you for your nice technical information. Actually, I want to observe some aging effect on the LUTs by giving them some electrical (DC0 or DC1) and high-temperature stress. I have already got some data where I have implemented a benchmark circuit on the particular area of the FPGA and applied that stresses on the FPGA. Since then, I have taken frequency by ring oscillator to observe the aging condition of the benchmark part and other unused parts. Before giving stress I have taken frequency from all the LUTs of the FPGA. However, the problem what I found that after aging not only degraded the used part but also degraded significantly other unused parts where there was no benchmark component during the stress. 

Actually, my assumption is that the aging mechanism also worked on the other unused part due to the initial value of the LUT 1'b0. You know Inside LUT, there is CMOS circuit and if the initial value is 1'b0 then aging mechanism NBTI is occurring automatically when faced with high temperature. That is the main reason why I want to force all LUTs /register initial value 1'b1 during power-up so that aging effect only occurs in the specific benchmark circuit area.

Previously, Xilinx had some direction in this regard using ISE version but I am using Vivado tools. Please see the below Xilinx link:

https://www.xilinx.com/support/answers/3123.html

https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/destech/html/cd_webpackcontrolling_register_initial_states.html

Sorry, I do not know whether my explanation and query are understandable or not. Actually, It will be better for me to know how to give constantly DC Logic 1 stress on to all LUTs of the FPGA.

Thanks and regards,

Foisal Ahmed

 

[jpeyron]

Hi @Foisal Ahmed,

I have not setup a project like this. I would suggest to look through the  7 Series FPGAs Configurable Logic Block User Guide. I would also reach out to xilinx support as well.

thank you,

Jon