• 0

Arty7 xemacp undeclared


Question

I'm having an issue following the example here:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start

The error is:

'xemacp' undeclared (first use in this function); did you mean 'xemac'? arty_ethernet_000_bsp line 347 C/C++ Problem

 

I tracked it down to this line:

https://github.com/Xilinx/embeddedsw/blob/0c6cd096c8f81978854c782c7aa175241fc3af20/ThirdParty/sw_services/lwip202/src/contrib/ports/xilinx/netif/xadapter.c#L347

 

It's failing because neither 'XLWIP_CONFIG_INCLUDE_GEM' nor 'XLWIP_CONFIG_INCLUDE_AXI_ETHERNET' are defined a few lines above that.

 

Is there a config option I missed?

Link to post
Share on other sites

9 answers to this question

Recommended Posts

  • 0

Hi @zthom,

First i would right click on the bsp and re-generate the board support package. If that does not fix the error delete the bsp and create another bsp with the exact name. If that does not fix the error please attach a screen shot of the Vivado block design and the SDK with you error. Are you using the Arty-A7 board files? Which Arty-A7 are you using the 35T or the 100T? What version of Vivado are you using?

cheers,

Jon

Link to post
Share on other sites
  • 0

Hello jpeyron.

I tried to re-generate bsp and created another project. I am using official Arty-A7 files from Digilentinc github, it is 100T. 

I have Vivado 2018.2

In the tutorial, they are using lwip 1.4 and I am using lwip 2.2 - SDK does not offer me the old version. I have followed exactly the tutorial, event with experiments, there is a problem with compiling lwip. Without lwip, bsp can compile.

Here is block design:

image.thumb.png.51fed456f8f56894caa6f4df9636ce99.png

 

And errors:

image.png.87ab2c487248391e7d0f6720b2653167.png

Link to post
Share on other sites
  • 0

This appears to be a known issue in 2018.2: https://www.xilinx.com/support/answers/71330.html. It appears that support for the emaclite driver got missed in a change (https://github.com/Xilinx/embeddedsw/commit/16c05f56fcb860513d34b83a1a301fa185e06316).

Their patch can't actually be applied to Xilinx/SDK/2018.2/data/embeddedsw, but the changes are small and easy to make. I've attached the file here. It should replace ThirdParty/sw_services/lwip202_v1_1/src/contrib/ports/xilinx/netif/xadapter.c. Then you can regenerate the BSP sources and it will compile.

xadapter.c

Link to post
Share on other sites
  • 0

Hi @neha,

I would first re-generate the board support package by right clicking on the applications bsp. If that does not fix the error then delete the bsp and create another with the exact name.  Can you attach a screen shot of your block design in vivado?

thank you,

Jon

 

 

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now