Arty-Z7 20: HDMI pass-through project black screen

[qarlosalberto]

Hello,

I have created a HDMI pass-through project with Arty-Z7 20 and Vivado 2017.4. I connect a HDMI camera in the input and a screen in the output, but I have a black screen :(

- dvi2rgb: >=120 Mhz (1080p)

- clk_in1: 125Mhz

- clk_out1: 200Mhz

 

This is my project:

 

And my xdc:

##HDMI RX Signals

set_property -dict { PACKAGE_PIN P19   IOSTANDARD TMDS_33  } [get_ports { TMDS_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
set_property -dict { PACKAGE_PIN N18   IOSTANDARD TMDS_33  } [get_ports { TMDS_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
create_clock -period 6.734 -waveform {0 3.367} [get_ports { TMDS_clk_p }];
set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_n[0]}]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_p[0]}]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_n[1]}]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_p[1]}]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_n[2]}]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33  } [get_ports { TMDS_data_p[2]}]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_hpd_tri_o[0] }]; #IO_25_34 Sch=HDMI_RX_HPD
set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { DDC_scl_io }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { DDC_sda_io }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA

##HDMI TX Signals

set_property -dict { PACKAGE_PIN L17   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
set_property -dict { PACKAGE_PIN L16   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
set_property -dict { PACKAGE_PIN K18   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
set_property -dict { PACKAGE_PIN K17   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_p[0]  }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
set_property -dict { PACKAGE_PIN J19   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_n[1]  }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
set_property -dict { PACKAGE_PIN K19   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_p[1]  }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
set_property -dict { PACKAGE_PIN H18   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_n[2]  }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
set_property -dict { PACKAGE_PIN J18   IOSTANDARD TMDS_33  } [get_ports { TMDS_1_data_p[2]  }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P


set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }]; 

Thank you :)

 

 

 

[askhunter]

@kwilber you are awesome!

[kwilber]

The warning you pasted is benign and simply means there are no ILAs present in your design.

The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design. 

Finally, @elodg gives some great troubleshooting information in this thread.

[askhunter]

Hi I have a new problem. I try to hdmi pass-throug. From my laptop to monitor. Bu I got an warning massage. It didn't work. I hope someone can help mi. Also I am using pynq z2 and all pins same with arty z7 -20.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[askhunter]

• @kwilber I done it. I forgot " generate block design ".  thank you for all help.

[askhunter]

 

 

Thanks for your reply.. I'm sorry I'm stealing your time,@kwilber

[kwilber]

Can you paste the latest error messages?

Can you also paste the module definition from your design wrapper? From the error message you pasted earlier,  It has separate ports for the DDC_scl_io_i, DDC_scl_io_o nd DDC_scl_io_t, DDC_sda_io_i, DDC_sda_io_o nd DDC_sda_io_t.

The module definition vivado created for the design I just did for you (using ports named hdmi_in and hdmi_out) looks like

[askhunter]

I did what you said but I got the same error. Thanks for your help. I hope we can solve the problem.

 

 

[kwilber]

In your constraint file, the ddc pins have lowercase "ddc_scl_io" and "ddc_sda_io". Your block design has the port in uppercase "DDC". The case must match. Try editing your constraint file to have "DDC_scl_io" and "DDC_sda_io".

[askhunter]

I got an error message. According to the reference here, I created the constant file. what can I do?

Thank you . Best regards.

 

 

 

[kwilber]

I see where your question comes from... the Arty Z7-20 board file does not define the hdmi ports so they are not available in the Board window.

In that case, you can use "Make External". For example, once you place the rgb2dvi IP on the block design, you can right click on its TMDS port and select "Make External" from the context menu.

Vivado will add the port and assign a default name.

To rename the port, left click on it and in the "External Interface Properties" window, type hdmi_out. The block design will update with the updated name.

You can follow the same process to add the dvi2rgb IP and create the hdmi_in and hdmi_in_ddc ports.

Your project will need a constraints file with the pin names set to match those in the block design.

[kwilber]

@askhunter,

Are you asking how I created and named the hdmi_in and hdmi_out ports in the block design for my Zybo-Z7 project?

If so, once I started a new project selecting the Zybo-Z7-20, I created an empty block design. I then selected the "Board" window. The Zybo-Z7-20 and its available components were listed. 

Under the HDMI branch, I double clicked on the "HDMI in" component and clicked on OK in the dialog that popped up.

The DVI to RGB IP block was added to my block design along with the appropriate ports.

I did the same thing for the "HDMI out" component.

I did the same thing for the system clock component. Then I ran block automation to add the reset line then added connections between the blocks as necessary and ended up with this.

 

[jpeyron]

Hi @askhunter,

Both the  Zybo-Z7 and the Arty-Z7 have an HDMI IN and a HDMI OUT port that are not bi-directional. The Arty-Z7 and the Zybo-Z7 only have the physical hardware to provide the described function I.E. HDMI In and HDMI out. So as an example,  you would not be able to use the HDMI IN port as an HDMI OUT port instead. The  original Zybo has a HDMI I/O. The HDMI I/O can be used for either hdmi input or hdmi output but not both input and output at the same time.

thank you,

Jon

[askhunter]

On 8/23/2018 at 2:24 AM, kwilber said:

I have a similar project done with Vivado 2016.4 working on a Zybo Z7.

You might try adding a Hot Plug Detect as shown in my block design. The constant block value is set to 1.

My design was connected to a GoPro4 set to 720p so my rgb2dvi used <80Mhz (720p) and rgb2dvi was set to 1280x720 and <120Mhz. My clk_in1 and clk_out1 were the same as yours.

 

someone can explaint that how can i create hdmi in and hdmi out port? like master port. 

[qarlosalberto]

Thanks to both of you, I have added a Hot Plug Detect and now it runs :) :) :) :)

[kwilber]

I re-targeted my design for the Arty-Z7 and upgraded the project to Vivado 2017.4.

I can verify the design functions.

The image below shows the GoPro focused on the Arty and the image displayed on the monitor. It takes the GoPro maybe 15 seconds once you plug in the hdmi cable before it starts outputting the image.

Let me know if you want me to upload the project archive.

[kwilber]

I have a similar project done with Vivado 2016.4 working on a Zybo Z7.

You might try adding a Hot Plug Detect as shown in my block design. The constant block value is set to 1.

My design was connected to a GoPro4 set to 720p so my rgb2dvi used <80Mhz (720p) and rgb2dvi was set to 1280x720 and <120Mhz. My clk_in1 and clk_out1 were the same as yours.