Can't boot ZYBO from QSPI Flash

[shahbaz]

Hi,

I'm working on ZYBO SoC. I want to boot it from QSPI flash but it fails anyhow. I have tried two methods using Vivado and IMPACT tool.

 

1. After successful implementation I created .bit and .bin files for a simple led_blinky project. Than I added "Configuration Memory Device" and selected Spansion s25fl128s 3.3v flash. I loaded the .bin file and then Erased, Verify and Programmed the flash step by step by checking the checkbox. The problem is with verify step. It fails every time. even then if I program it ignoring the failed verify step, it obliviously doesn't boots the program and no led blinks on board after resetting it.

PS: I've taken care of the Jumpers already.

 

2. In the iMPACT tool I first created the PROM for a single FPGA, added 128MiB and created a .mcs file from the .bit file. then I initialized chain and after successful detection of board I added SPI Flash (which is attached above the ARM in the workspace figure) and loaded the flash with .mcs file. than I get option to either Erase, Verify or Program the flash. here too the program fails at Verify Step.

 

Please help out. 

[jpeyron]

Hi @shahbaz,

 

I believe your error is due to not having a zynq processor or IPI in your project. If you are trying to program the flash with Verilog module the steps should be as follows:

1. create a base zynq design and verify. (create block diagram, add zynq core, run block automation, connect FCLK_CLK0 to M_AXI_GP0_ACLK)

2. generate the top wrapper from the block design and don't let vivado auto update the wrapper. 

4. edit the top file to include your HDL module

5. generate bitstream

6. file -> export -> hardware (include bitstream)

7. open sdk

8. file-> new -> application project

9. select FSBL and create project

10.  Xilinx tools-> create boot image

11. choose file output location

12. add file -> <FSBL>.debug/<FSBL>.elf'

13. add file ->  hardware platform/.bit

14. click ok

15. xilinx tools -> program flash and choose your exported .bin file

16. switch jumper to qspi and reset board

Here is a completed zybo_pl_flash project done in Vivado 2015.4. All you should have to do to is load the project into vivado, launch sdk and program flash memory as described in step 4.4 in this tutorial. 

thank you,

Jon

[jpeyron]

Hi @shahbaz,

Here is a forum thread discussing using the QSPI Flash on the Zybo. The forum thread has a step by step description of the process.  Here is "QSPI Flash Support Guide- Guidelines to check QSPI Flash compatibility with Zynq" that might be helpful as well.

thank you,

Jon

[shahbaz]

@jpeyron thanks for the concern, I tried that solution. but its not helpful while working on Vivado using Verilog Language. I precisely needed solution for Vivado 15.4 and I'm working on Verilog for ZYBO

[jpeyron]

Hi @shahbaz,

My understanding is that you need to use the PS with sdk  when programming the flash on development boards that have the ZYNQ processor like the Zybo. The flash is connected directly to the ZYNQ Processor. The flash can not be programmed from the Vivado hardware manager but instead by SDK. Here is the Zedboard Programming Guide in SDK tutorial that should be easily altered to work with the Zybo. When using the Appendix A. Creating a boot image in SDK(since your design is purely uses the PL, a project elf file is not required for the boot image). We do not have a tutorial specifically using Vivado 2015.4 but the the linked tutorial should still be the same overall process.

thank you,

Jon

[shahbaz]

please help me out at launching SDK. I try to launch it under the File menu button, a window "Launch SDK" opens asking for Export Location. what do I have to do there. it gives error "An exported file for this module is not found at this location. Choose another export location or export design and launch SDK"

[jpeyron]

Hi @shahbaz,

To clarify, previous to trying to launch SDK from vivado you were able to generate a bitstream and you exported the hardware including the bitstream.  Please attach screen shots of your error. What is the path to your project? What Operating System is your PC? 

thank you,

Jon

 

[shahbaz]

Yes, I generated .bit file but when I tried to Export Hardware along with bit file it failed (picture attached), though it exports successfully export without including .bit file

Project path is C:\Users\LENOVO\Documents\Vivado\slow_clk\

And I'm running Windows 10

[shahbaz]

Hi @jpeyron

can you please help me out with step 12 and 13, when I add these files, the windows also asks me for partition type. I added the .bit file but where can I find the .elf fie? I looked for it but I cant find that "bootloader" mentioned in step A.3 of appendix A of attached tutorial. 

[jpeyron]

Hi ,@shahbaz

I attached screen shots of where the files for step 12 and 13 are in the project i linked you to as well as where the boot.bin is. Step 4 of the tutorial linked above is the sdk portion of the steps, step 7 and above,  in the previous post . I also attached screen shots of the xdc and hdl code and how it looks in the sources tab. The block design consists of the Zynq processor left on the default(using board files) when doing the block automation. The FCLK_CLK0 needs to be connected to the M_AXI_GP0_ACLK.

thank you,

Jon

 

 

 

[shahbaz]

hi @jpeyron

Thank you for you concern. I couldn't find because I was choosing wrong board (selecting the part instead) and I missed the step for unchecking the auto update wrapper. found it in destined folder once I selected the right board.

[jpeyron]

Hi @shahbaz,

Glad to hear you found the issue. Thank you for sharing what was wrong.

cheers,

Jon

[mnt]

 

Hi,

I am trying to do the steps as mentioned previously and I am not able to insert the VHDL module (a file) inside the wrapper - step 4. Follows screen image as is. It includes as a second design.

Could anyone tell me what procedure should I perform to make a vhd file be included in the top file (design_1 wrapper).

thank you

[jpeyron]

Hi @mnt,

Welcome to the Digilent forums!

Are you trying to add a VHDL entity to a zynq processor block design?

If that is a yes then right click on an empty portion of the block design and select add a module.

Then select the VHDL file. Here is a good YouTube video about this process.

best regards,

Jon