[Vivado 12-1411] Cannot set LOC property of ports, Terminal usb_uart_txd cannot be placed on C4 (IOB_X1Y136) because the pad is already occupied by terminal usb_uart_rxd

[Shaw]

Hello,

I am using Vivado 2017.3, and creating a block design.

In this design, I added a AXI Uartlite module, like this:

There are two external interfaces: usb_uart_rxd and usb_uart_txd. After I add constraints and run implementation, there are two critical warnings:

What is the reason for this? And what should I do?

Thanks.

[jpeyron]

Hi @Shaw,

In your block design it appears that you are using the usb uart from the board tab which are from the Nexys 4 DDR board files. The board files automatically handles the constraints for the usb uart.  I would suggest to remove the uart portion on the XDC.  Let us know if the errors persist. Below I have attached screen shots of the uart being connected through the board tab using the board files and using the Uartlite IP Core, right-clicking on the uart and selecting make external. 

thank you,

Jon

[jpeyron]

Hi @Shaw,

Does your development board have a zynq processor? Here is a forum thread that discusses a similar error.  Could you attach a screen shot of your full block design, wrapper file and xdc file. What Development board are you using?

thank you,

Jon

[Shaw]

On 8/18/2018 at 12:39 AM, jpeyron said:

Hi @Shaw,

Does your development board have a zynq processor? Here is a forum thread that discusses a similar error.  Could you attach a screen shot of your full block design, wrapper file and xdc file. What Development board are you using?

thank you,

Jon

Thank you for your help!

I'm using Nexys4 DDR, and the processor is a simple CPU designed by myself. Block design diagram is here:

wrapper file is here:

xdc file is here:

[Shaw]

Hi @jpeyron,

Thanks for your reply, it solved my problem successfully.