The good news is I continued my experiments with CoraZ7-10 and Vivado (2017 + 2018). Unfortunately I stumbled upon some errors and things I don't really comprehend...
I modified the constraints file Cora-Z7-10-Master.xdc to allow access to leds and buttons like shown below:
My design looks like this (I followed your tutorial):
1) Trying to create the bitstream I receive first two warnings:
error: PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values
error: PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values
2) And then two errors:
[DRC NSTD-1] Unspecified I/O Standard: 6 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value...
[DRC UCIO-1] Unconstrained Logical Port: 6 out of 138 logical ports have no user assigned specific location constraint (LOC)...
Both are related to rgb_leds_tri_o[5:0].
Inspecting the Bus properties, I noticed:
Which has nothing to do with the way , the signals are defined in the constraints file (led0_b, etc.) or with the actual PACKAGE_PIN defined in part0_pins.xml.
How can I make the correct connections? What am I overlooking now?
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radug
Hello guys,
The good news is I continued my experiments with CoraZ7-10 and Vivado (2017 + 2018). Unfortunately I stumbled upon some errors and things I don't really comprehend...
I'm using the same tutorial (https://reference.digilentinc.com/vivado/getting-started-with-ipi/start).
I modified the constraints file Cora-Z7-10-Master.xdc to allow access to leds and buttons like shown below:
My design looks like this (I followed your tutorial):
1) Trying to create the bitstream I receive first two warnings:
error: PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values
error: PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values
2) And then two errors:
[DRC NSTD-1] Unspecified I/O Standard: 6 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value...
[DRC UCIO-1] Unconstrained Logical Port: 6 out of 138 logical ports have no user assigned specific location constraint (LOC)...
Both are related to rgb_leds_tri_o[5:0].
Inspecting the Bus properties, I noticed:
Which has nothing to do with the way , the signals are defined in the constraints file (led0_b, etc.) or with the actual PACKAGE_PIN defined in part0_pins.xml.
How can I make the correct connections? What am I overlooking now?
PS I tried what is suggested here https://www.xilinx.com/support/answers/56354.html but, in this case, the application created with the SDK (see next point) does not work.
3) Launch SDK
First I noticed here that if one generates the main.c file in /Src directory (as shown in the tutorial) the application cannot be compiled:
The solution is to move the main.c file to the application directory (cora_z7_test). Then the application can be successfully compiled.
But the application does not work - I suppose - because the pins/ports are mapped incorrectly (see point 2).
Best regards,
Radu G.
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