Zybo: Routing USB pins to EMIO

[jelicicm]

Hello all,

I'm trying to build a project on my Zybo where I would route both USB and Ethernet signals trough my PL, instead of them going directly to PS. Now, to my understanding, what I should do is route those signals trough EMIO ports on Zynq. Looking trough Zybo datasheet I see that USB signals such as OTG_DATA[7:0], OTG_NXT, OTG_STP and so on are routed to pins: A14, D15, A12 and so on. So, per my understanding of using EMIO pins, I should be able to put those values in XDC file and Vivado would route those signals trough EMIO. When I open Net View, I see all the signals I expect to see: ulpi_data_io[7:0], ulpi_clk, and so on. So I want to set up those nets to be routed to my selected pins.
However, when I try to input values found in Zybo datasheet, Vivado won't let me select some of the pins, it says that location is unavailable. 

Am I doing something wrong? What is the correct way of assigning USB and Ethernet pins to EMIO port, instead of them being routed to PS by default?

Thank you.

Best regards,
jelicicm

[xc6lx45]

Hi,
I suspect it is not possible, see
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
page 48 table 2.3

USB [0,1] ... EMIO Routing: Not available

and previous page
The I/O peripheral signals can also be routed to the PL (including PL device pins) through the EMIO interface

Disclaimer: !'ve spent about 15 seconds thinking about this, better double-check.

[jpeyron]

Hi @jelicicm,

You can connect the Zynq PS side MAC to either the MIO pins ( which is how Ethernet is generally done for Zynq based boards ) using an RGMII interface or to the EMIO and through the PL using a GMII or SGMII interface. When going through the PL you need to supply your own PHY.  My understanding is that you would have to connect an external Ethernet PHY to the PL pins and hook it up to the ARM MAC through the EMIO. Since there are two Ethernet controllers in the PS you can have 2 Ethernet adaptors this way even if your board only has one PHY connected to MIO pins.

If you want to use you own MAC expressed in logic on the PL side you could do that, memory map the custom MAC control registers and DMA data using the AXI interconnects into the PS memory and create your own drivers to operate it.  

The USB host functionality on the Zybo runs between the multiplexed IO at the ARM processor to an IC at the USB OTG port. The communication between this PHY and the processor is not something that I would recommend trying to develop yourself. Unfortunately, that functionality has not been implemented.  The fastest way to getting USB and ethernet peripherals interfaced with the board would be to run an embedded Linux image on it, for which there already exists drivers that would handle communication with ethernet and various USB peripheral devices (something through PetaLinux would be quick to implement). Here is the resource center for the zybo. Here is the Petalinux Support for Digilent Boards which has multiple versions of petalinux project.

thank you,

Jon

[jelicicm]

Hello @jpeyron and thank you very much for your reply!

What I wanted was to use AXI USB 2.0 Device Controller (PG137) as a USB IP, and avoid doing much with PS side. Sadly, now I see that is not possible with Zybo, or one other custom board my company made, because USB PHY is connected to bank 501, which can only be accessed trough PS, and can't be used in PL in any way.

I will simply have to use PS to use USB functionality.

Thanks again for your help.

Best regards,
jelicicm

 

@xc6lx45 15 seconds was more than enough, you were absolutely correct. Thanks for your answer!

[jamey.hicks]

I've never tried this, but I believe that your logic can communicate via AXI to the built-in USB controller, which can operate in device mode. This would take fewer PL resources than using the AXI USB 2.0 Device Controller.

To do so, you'll need to remove the USB controller from the device tree file used to boot Linux so that only your PL would be using the USB controller.